#if (FEATURE_MODE == 0)
/**
 @file sys_usw_monitor.c

 @date 2009-10-19

 @version v2.0

 The file contains all monitor APIs of sys layer
*/

/***************************************************************
 *
 * Header Files
 *
 ***************************************************************/
#include "sal.h"
#include "ctc_debug.h"
#include "ctc_error.h"

#include "sys_usw_common.h"
#include "sys_usw_chip.h"

#include "sys_usw_monitor.h"
#include "sys_usw_dma.h"
#include "sys_usw_dmps.h"
#include "sys_usw_wb_common.h"
#include "sys_usw_register.h"
#include "sys_usw_qos_api.h"

#include "drv_api.h"

/***************************************************************
 *
 *  Defines and Macros
 *
 ***************************************************************/
#define SYS_MONITOR_GET_CHANNEL(lport)  SYS_MAP_DRV_LPORT_TO_SYS_LPORT(lport)

#define SYS_MONITOR_LATENCY_MAX_THRD (0xFFFFFFFF << 5)
#define SYS_MONITOR_PRIO_CLASS_NUM_MAX  8
#define SYS_MONITOR_BUFFER_MAX_THRD ((1<<14)-1)
#define SYS_MONITOR_QWM_TYPE_MAX  3
#define SYS_MONITOR_EXT_MSG_CNT_MAX   3   /*for erm buffer event*/
#define SYS_MONITOR_INIT_CHECK() \
    do { \
        LCHIP_CHECK(lchip); \
        if (NULL == p_usw_monitor_master[lchip]){ \
            return CTC_E_NOT_INIT;\
        } \
    } while (0)

#define SYS_CHAN_BITMAP_IN_WORD   16    /*chan bitmap*/
#define SYS_CHAN_BITMAP_IN_WORD_DP   4    /*chan bitmap per dp*/

sys_monitor_master_t *p_usw_monitor_master[CTC_MAX_LOCAL_CHIP_NUM_PP] = {NULL};

STATIC int32
_sys_usw_monitor_set_queue_watermark_cfg(uint8 lchip, ctc_monitor_glb_cfg_t*p_cfg)
{
    uint32 cmd = 0;
    uint16 queue_id[SYS_MONITOR_QWM_NUM_MAX]  = {0};
    uint16 queue_id_tmp = 0;
    uint8 queue_cnt_real = 0;
    uint8 index = 0;
    uint8 index1 = 0;
    uint8 is_repeat = 0;
    uint16 channel_id = 0;
    uint8 step = 0;
    uint32 value[3] = {0};

    if (DRV_FROM_AT(lchip))
    {
        return CTC_E_NOT_SUPPORT;
    }
    else if ((DRV_IS_TMM(lchip) || DRV_IS_TMG(lchip)))
    {
        ErmResrcMaxMonCtl_m max_ctl;
        CTC_MAX_VALUE_CHECK(p_cfg->u.qwm.queue_cnt, SYS_MONITOR_QWM_NUM_MAX);
        for(index = 0; index < p_cfg->u.qwm.queue_cnt; index++)
        {
            is_repeat = 0;
            CTC_ERROR_RETURN(sys_usw_qos_queue_get_queue_id(lchip, &p_cfg->u.qwm.queue_list[index], &queue_id_tmp));

            /* check repeat */
            for(index1 = 0; index1 < queue_cnt_real; index1++)
            {
                if(queue_id[index1] == queue_id_tmp)
                {
                    is_repeat = 1;
                    break;
                }
            }

            if(!is_repeat)
            {
                queue_id[queue_cnt_real++] = queue_id_tmp;
            }
        }
        sal_memset(&max_ctl, 0, sizeof(max_ctl));
        if(p_cfg->u.qwm.queue_cnt)
        {
            step = ErmResrcMaxMonCtl_array_1_resrcMaxMonQueueId_f - ErmResrcMaxMonCtl_array_0_resrcMaxMonQueueId_f;
            for(index = 0; index < queue_cnt_real; index++)
            {
                SetErmResrcMaxMonCtl(V, array_0_resrcMaxMonQueueId_f + index * step, &max_ctl, queue_id[index]);
                CTC_BIT_SET(value[0], index);
            }
            SetErmResrcMaxMonCtl(V, resrcMaxMonEn_f, &max_ctl, value[0]);
        }
        cmd = DRV_IOW(ErmResrcMaxMonCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &max_ctl));
    }
    else
    {
        ds_t ds;
        uint8 value_tmp[SYS_MONITOR_QWM_TYPE_MAX] = {0}; /*type:0:chan,1:extend grp,2:dma*/
        uint8 valid_tmp[SYS_MONITOR_QWM_TYPE_MAX] = {0};
        CTC_MAX_VALUE_CHECK(p_cfg->u.qwm.queue_cnt, (MCHIP_CAP(SYS_CAP_QOS_QUEUE_NUM_PER_CHAN) +
            MCHIP_CAP(SYS_CAP_QOS_MISC_QUEUE_NUM) + MCHIP_CAP(SYS_CAP_QOS_QUEUE_NUM_PER_EXT_GRP) + 1));

        for(index = 0; index < p_cfg->u.qwm.queue_cnt; index++)
        {
            is_repeat = 0;
            CTC_ERROR_RETURN(sys_usw_qos_queue_get_queue_id(lchip, &p_cfg->u.qwm.queue_list[index], &queue_id_tmp));

            if (SYS_IS_NETWORK_BASE_QUEUE(queue_id_tmp) || SYS_IS_NETWORK_CTL_QUEUE(queue_id_tmp) || SYS_IS_MISC_CHANNEL_QUEUE(queue_id_tmp))
            {
                CTC_ERROR_RETURN(sys_usw_qos_get_channel_by_queue_id(lchip, queue_id_tmp, &channel_id));
                if(!valid_tmp[0] && channel_id < MCHIP_CAP(SYS_CAP_NETWORK_CHANNEL_NUM))
                {
                    value_tmp[0] = channel_id;
                    valid_tmp[0] = 1;
                }
                else if(value_tmp[0] != channel_id)
                {
                    return CTC_E_INVALID_PARAM;
                }
            }
            else if(SYS_IS_EXT_QUEUE(queue_id_tmp))
            {
                value[0] = (queue_id_tmp - MCHIP_CAP(SYS_CAP_QOS_QUEUE_BASE_EXT)) / MCHIP_CAP(SYS_CAP_QOS_QUEUE_NUM_PER_EXT_GRP);
                if(!valid_tmp[1])
                {
                    value_tmp[1] = value[0];
                    valid_tmp[1] = 1;
                }
                else if(value_tmp[1] != value[0])
                {
                    return CTC_E_INVALID_PARAM;
                }
            }
            else if(SYS_IS_CPU_QUEUE(queue_id_tmp))
            {
                if(!valid_tmp[2])
                {
                    value_tmp[2] = queue_id_tmp;
                    valid_tmp[2] = 1;
                }
                else if(value_tmp[2] != queue_id_tmp)
                {
                    return CTC_E_INVALID_PARAM;
                }
            }
        }

        /*basic/ctl queue*/
        cmd = DRV_IOR(ErmResrcMonScanCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
        value[0] = GetErmResrcMonScanCtl(V, resrcMonScanPushPortDetailedEn_f, ds);

        cmd = DRV_IOR(ErmResrcMonPortCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
        value[1] = GetErmResrcMonPortCtl(V, resrcMonPortEn_f, ds);
        value[2] = GetErmResrcMonPortCtl(V, resrcMonPortId_f, ds);

        if(value[0] && ((valid_tmp[0] && value[1] && value[2] != channel_id) || !valid_tmp[0]))/*port scan enable*/
        {
            return CTC_E_PARAM_CONFLICT;
        }

        SetErmResrcMonPortCtl(V, resrcMonPortEn_f, ds, valid_tmp[0]);
        SetErmResrcMonPortCtl(V, resrcMonPortId_f, ds, valid_tmp[0] ? value_tmp[0] : 0);
        cmd = DRV_IOW(ErmResrcMonPortCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));

        /*extend queue*/
        cmd = DRV_IOR(ErmResrcMonGroupCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
        SetErmResrcMonGroupCtl(V, resrcMonGroupEn_f, ds, valid_tmp[1]);
        SetErmResrcMonGroupCtl(V, resrcMonGroupId_f, ds, valid_tmp[1] ? value_tmp[1] : 0);
        cmd = DRV_IOW(ErmResrcMonGroupCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));

        /*dma queue*/
        value[0] = queue_id_tmp - MCHIP_CAP(SYS_CAP_QOS_QUEUE_BASE_EXCP);
        cmd = DRV_IOR(ErmResrcMonDmaCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
        SetErmResrcMonDmaCtl(V, resrcMonDmaEn_f, ds, valid_tmp[2]);
        SetErmResrcMonDmaCtl(V, resrcMonDmaQueId_f, ds, valid_tmp[2] ? value_tmp[2] : 0);
        cmd = DRV_IOW(ErmResrcMonDmaCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));

    }

    return CTC_E_NONE;
}

STATIC int32
_sys_usw_monitor_get_queue_watermark_cfg(uint8 lchip, ctc_monitor_glb_cfg_t*p_cfg)
{
    uint8  index = 0;
    uint8  index_end = 0;
    uint8  step = 0;
    uint8  queue_cnt_tmp = 0;
    uint16 queue_id = 0;
    uint32 cmd = 0;
    uint32 value1 = 0;
    uint32 value2 = 0;
    ctc_qos_queue_id_t queue[SYS_MONITOR_QWM_NUM_MAX];
    CTC_MAX_VALUE_CHECK(p_cfg->u.qwm.queue_cnt, SYS_MONITOR_QWM_NUM_MAX);
    sal_memset(queue, 0, sizeof(queue));

    if(DRV_FROM_AT(lchip))
    {
        return CTC_E_NOT_SUPPORT;
    }
    else if((DRV_IS_TMM(lchip) || DRV_IS_TMG(lchip)))
    {
        ErmResrcMaxMonCtl_m max_ctl;
        cmd = DRV_IOR(ErmResrcMaxMonCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &max_ctl));
        value1 = GetErmResrcMaxMonCtl(V, resrcMaxMonEn_f, &max_ctl);
        step = ErmResrcMaxMonCtl_array_1_resrcMaxMonQueueId_f - ErmResrcMaxMonCtl_array_0_resrcMaxMonQueueId_f;
        for(index = 0; index < SYS_MONITOR_QWM_NUM_MAX; index++)
        {
            if(CTC_IS_BIT_SET(value1, index))
            {
                queue_id = GetErmResrcMaxMonCtl(V, array_0_resrcMaxMonQueueId_f + index * step, &max_ctl);
                CTC_ERROR_RETURN(sys_usw_qos_queue_id_get_queue(lchip, &queue[index_end++], queue_id));
            }
        }
    }
    else
    {
        ds_t ds;
        /*basic/ctl queue*/
        cmd = DRV_IOR(ErmResrcMonPortCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
        value1 = GetErmResrcMonPortCtl(V, resrcMonPortEn_f, ds);
        value2 = GetErmResrcMonPortCtl(V, resrcMonPortId_f, ds);

        if(value1)
        {
            for(index = 0; index < MCHIP_CAP(SYS_CAP_QOS_QUEUE_NUM_PER_CHAN) + MCHIP_CAP(SYS_CAP_QOS_MISC_QUEUE_NUM); index++)
            {
                if(index >= MCHIP_CAP(SYS_CAP_QOS_QUEUE_NUM_PER_CHAN))
                {
                    queue_id = index - MCHIP_CAP(SYS_CAP_QOS_QUEUE_NUM_PER_CHAN) + MCHIP_CAP(SYS_CAP_QOS_QUEUE_BASE_NETWORK_MISC)
                        + (value2 * MCHIP_CAP(SYS_CAP_QOS_MISC_QUEUE_NUM));
                }
                else
                {
                    queue_id = value2 * MCHIP_CAP(SYS_CAP_QOS_QUEUE_NUM_PER_CHAN) + index;
                }
                CTC_ERROR_RETURN(sys_usw_qos_queue_id_get_queue(lchip, &queue[index_end], queue_id));
                if(index >= MCHIP_CAP(SYS_CAP_QOS_QUEUE_NUM_PER_CHAN) && queue[index_end].queue_id == 0)
                {
                    sal_memset(&queue[index_end], 0, sizeof(ctc_qos_queue_id_t));
                }
                else
                {
                    index_end = index_end + 1;
                }
            }
        }
        /*extend queue*/
        cmd = DRV_IOR(ErmResrcMonGroupCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
        value1 = GetErmResrcMonGroupCtl(V, resrcMonGroupEn_f, ds);
        value2 = GetErmResrcMonGroupCtl(V, resrcMonGroupId_f, ds);

        if(value1)
        {
            for(index = 0; index < MCHIP_CAP(SYS_CAP_QOS_QUEUE_NUM_PER_EXT_GRP); index++)
            {
                queue_id = MCHIP_CAP(SYS_CAP_QOS_QUEUE_BASE_EXT) + value2 * MCHIP_CAP(SYS_CAP_QOS_QUEUE_NUM_PER_EXT_GRP) + index;
                CTC_ERROR_RETURN(sys_usw_qos_queue_id_get_queue(lchip, &queue[index_end++], queue_id));
            }
        }
        /*dma queue*/
        cmd = DRV_IOR(ErmResrcMonDmaCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
        value1 = GetErmResrcMonDmaCtl(V, resrcMonDmaEn_f, ds);
        value2 = GetErmResrcMonDmaCtl(V, resrcMonDmaQueId_f, ds);

        if(value1)
        {
            queue_id = value2 + MCHIP_CAP(SYS_CAP_QOS_QUEUE_BASE_EXCP);
            CTC_ERROR_RETURN(sys_usw_qos_queue_id_get_queue(lchip, &queue[index_end++], queue_id));
        }

    }

    queue_cnt_tmp = p_cfg->u.qwm.queue_cnt > index_end ? index_end : p_cfg->u.qwm.queue_cnt;
    sal_memcpy(p_cfg->u.qwm.queue_list, queue, sizeof(ctc_qos_queue_id_t)*queue_cnt_tmp);
    p_cfg->u.qwm.queue_cnt = queue_cnt_tmp;

    return CTC_E_NONE;
}

STATIC int32
_sys_usw_monitor_get_queue_watermark(uint8 lchip, ctc_monitor_watermark_t *p_watermark)
{
    uint32 cmd = 0;
    uint32 field_value = 0;
    uint32 value[3] = {0};
    uint16 channel = 0;
    uint16 queue_id = 0;
    uint8 index = 0;
    uint8 step = 0;
    
    CTC_ERROR_RETURN(sys_usw_qos_queue_get_queue_id(lchip, &p_watermark->queue, &queue_id));

    if(DRV_FROM_TMM(lchip))
    {
         ErmResrcMaxMonCtl_m max_ctl;
         cmd = DRV_IOR(ErmResrcMaxMonCtl_t, DRV_ENTRY_FLAG);
         CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &max_ctl));
         field_value = GetErmResrcMaxMonCtl(V, resrcMaxMonEn_f, &max_ctl);

         step = ErmResrcMaxMonCtl_array_1_resrcMaxMonQueueId_f - ErmResrcMaxMonCtl_array_0_resrcMaxMonQueueId_f;
         for(index = 0; index < SYS_MONITOR_QWM_NUM_MAX; index++)
         {
             if(queue_id == GetErmResrcMaxMonCtl(V, array_0_resrcMaxMonQueueId_f + index * step, &max_ctl)
                 && CTC_IS_BIT_SET(field_value, index))
             {
                 p_watermark->u.buffer.max_total_cnt = GetErmResrcMaxMonCtl(V, array_0_resrcMaxMonQueueCnt_f + index * step, &max_ctl);
                 break;
             }
         }
    }
    else
    {
        ds_t ds;
        if (SYS_IS_NETWORK_BASE_QUEUE(queue_id) || SYS_IS_MISC_CHANNEL_QUEUE(queue_id) || SYS_IS_NETWORK_CTL_QUEUE(queue_id))
        {
            CTC_ERROR_RETURN(sys_usw_qos_get_channel_by_queue_id(lchip, queue_id, &channel));
            cmd = DRV_IOR(ErmResrcMonPortCtl_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
            value[0] = GetErmResrcMonPortCtl(V, resrcMonPortEn_f, ds);
            value[1] = GetErmResrcMonPortCtl(V, resrcMonPortId_f, ds);

            if(value[0] && value[1] == channel)
            {
                if(SYS_IS_NETWORK_CTL_QUEUE(queue_id))
                {
                    step = (DsErmResrcMonPortQueueMax_g2_1_netCtlQueCntMax_f - DsErmResrcMonPortQueueMax_g2_0_netCtlQueCntMax_f)
                             * (queue_id - MCHIP_CAP(SYS_CAP_QOS_QUEUE_BASE_NETWORK_MISC) - channel * MCHIP_CAP(SYS_CAP_QOS_MISC_QUEUE_NUM));
                    cmd = DRV_IOR(DsErmResrcMonPortQueueMax_t, DRV_ENTRY_FLAG);
                    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
                    p_watermark->u.buffer.max_total_cnt = GetDsErmResrcMonPortQueueMax(V, g2_0_netCtlQueCntMax_f + step, ds);
                }
                else
                {
                    step = (DsErmResrcMonPortQueueMax_g1_1_baseQueCntMax_f - DsErmResrcMonPortQueueMax_g1_0_baseQueCntMax_f) * p_watermark->queue.queue_id;
                    cmd = DRV_IOR(DsErmResrcMonPortQueueMax_t, DRV_ENTRY_FLAG);
                    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
                    p_watermark->u.buffer.max_total_cnt = GetDsErmResrcMonPortQueueMax(V, g1_0_baseQueCntMax_f + step, ds);
                }
            }
        }
        else if (SYS_IS_EXT_QUEUE(queue_id))
        {
            cmd = DRV_IOR(ErmResrcMonGroupCtl_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
            value[0] = GetErmResrcMonGroupCtl(V, resrcMonGroupEn_f, ds);
            value[1] = GetErmResrcMonGroupCtl(V, resrcMonGroupId_f, ds);
            value[2] = (queue_id - MCHIP_CAP(SYS_CAP_QOS_QUEUE_BASE_EXT)) / MCHIP_CAP(SYS_CAP_QOS_QUEUE_NUM_PER_EXT_GRP);

            if(value[0] && value[1] == value[2])
            {
                step = (DsErmResrcMonGroupQueueMax_g_1_extQueCntMax_f - DsErmResrcMonGroupQueueMax_g_0_extQueCntMax_f) * p_watermark->queue.queue_id;
                cmd = DRV_IOR(DsErmResrcMonGroupQueueMax_t, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
                p_watermark->u.buffer.max_total_cnt = GetDsErmResrcMonGroupQueueMax(V, g_0_extQueCntMax_f + step, ds);
            }
        }
        else if (SYS_IS_CPU_QUEUE(queue_id))
        {
            cmd = DRV_IOR(ErmResrcMonDmaCtl_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
            value[0] = GetErmResrcMonDmaCtl(V, resrcMonDmaEn_f, ds);
            value[1] = GetErmResrcMonDmaCtl(V, resrcMonDmaQueId_f, ds);
            value[2] = queue_id - MCHIP_CAP(SYS_CAP_QOS_QUEUE_BASE_EXCP);

            if (value[0] && value[1] == value[2])
            {
                cmd = DRV_IOR(DsErmResrcMonDmaQueueMax_t, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
                p_watermark->u.buffer.max_total_cnt = GetDsErmResrcMonDmaQueueMax(V, dmaQueCntMax_f, ds);
            }
        }
        else
        {
            return CTC_E_INVALID_PARAM;
        }
    }
    return CTC_E_NONE;
}


STATIC int32
_sys_usw_monitor_clear_queue_watermark(uint8 lchip, ctc_monitor_watermark_t *p_watermark)
{
    int32 cmd = 0;
    uint32 total_cnt = 0;
    uint32 field_value = 0;
    uint16 channel = 0;
    uint16 queue_id = 0;
    uint8 index = 0;
    uint8 step = 0;
    
    CTC_ERROR_RETURN(sys_usw_qos_queue_get_queue_id(lchip, &p_watermark->queue, &queue_id));

    if(DRV_FROM_TMM(lchip))
    {
        ErmResrcMaxMonCtl_m max_ctl;
        cmd = DRV_IOR(ErmResrcMaxMonCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &max_ctl));
        field_value = GetErmResrcMaxMonCtl(V, resrcMaxMonEn_f, &max_ctl);

        step = ErmResrcMaxMonCtl_array_1_resrcMaxMonQueueId_f - ErmResrcMaxMonCtl_array_0_resrcMaxMonQueueId_f;
        for(index = 0; index < SYS_MONITOR_QWM_NUM_MAX; index++)
        {
            if(queue_id == GetErmResrcMaxMonCtl(V, array_0_resrcMaxMonQueueId_f + index * step, &max_ctl)
                && CTC_IS_BIT_SET(field_value, index))
            {
                SetErmResrcMaxMonCtl(V, array_0_resrcMaxMonQueueCnt_f + index * step, &max_ctl, 0);
                cmd = DRV_IOW(ErmResrcMaxMonCtl_t, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &max_ctl));
                break;
            }
        }
    }
    else
    {
        uint32 value[3] = {0};
        ds_t ds;
        if (SYS_IS_NETWORK_BASE_QUEUE(queue_id) || SYS_IS_MISC_CHANNEL_QUEUE(queue_id) || SYS_IS_NETWORK_CTL_QUEUE(queue_id))
        {
            CTC_ERROR_RETURN(sys_usw_qos_get_channel_by_queue_id(lchip, queue_id, &channel));
            cmd = DRV_IOR(ErmResrcMonPortCtl_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
            value[0] = GetErmResrcMonPortCtl(V, resrcMonPortEn_f, ds);
            value[1] = GetErmResrcMonPortCtl(V, resrcMonPortId_f, ds);

            if(value[0] && value[1] == channel)
            {
                if (SYS_IS_NETWORK_CTL_QUEUE(queue_id))
                {
                    step = (DsErmResrcMonPortQueueMax_g2_1_netCtlQueCntMax_f - DsErmResrcMonPortQueueMax_g2_0_netCtlQueCntMax_f)
                             * (queue_id - MCHIP_CAP(SYS_CAP_QOS_QUEUE_BASE_NETWORK_MISC) - channel * MCHIP_CAP(SYS_CAP_QOS_MISC_QUEUE_NUM));
                    cmd = DRV_IOR(DsErmResrcMonPortQueueMax_t, DRV_ENTRY_FLAG);
                    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
                    SetDsErmResrcMonPortQueueMax(V, g2_0_netCtlQueCntMax_f + step, ds, total_cnt);
                    cmd = DRV_IOW(DsErmResrcMonPortQueueMax_t, DRV_ENTRY_FLAG);
                    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
                }
                else
                {
                    step = (DsErmResrcMonPortQueueMax_g1_1_baseQueCntMax_f - DsErmResrcMonPortQueueMax_g1_0_baseQueCntMax_f) * p_watermark->queue.queue_id;
                    cmd = DRV_IOR(DsErmResrcMonPortQueueMax_t, DRV_ENTRY_FLAG);
                    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
                    SetDsErmResrcMonPortQueueMax(V, g1_0_baseQueCntMax_f + step, ds, total_cnt);
                    cmd = DRV_IOW(DsErmResrcMonPortQueueMax_t, DRV_ENTRY_FLAG);
                    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
                }
            }
        }
        else if (SYS_IS_EXT_QUEUE(queue_id))
        {
            cmd = DRV_IOR(ErmResrcMonGroupCtl_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
            value[0] = GetErmResrcMonGroupCtl(V, resrcMonGroupEn_f, ds);
            value[1] = GetErmResrcMonGroupCtl(V, resrcMonGroupId_f, ds);
            value[2] = (queue_id - MCHIP_CAP(SYS_CAP_QOS_QUEUE_BASE_EXT)) / MCHIP_CAP(SYS_CAP_QOS_QUEUE_NUM_PER_EXT_GRP);

            if(value[0] && value[1] == value[2])
            {
                step = (DsErmResrcMonGroupQueueMax_g_1_extQueCntMax_f - DsErmResrcMonGroupQueueMax_g_0_extQueCntMax_f) * p_watermark->queue.queue_id;
                cmd = DRV_IOR(DsErmResrcMonGroupQueueMax_t, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
                SetDsErmResrcMonGroupQueueMax(V, g_0_extQueCntMax_f + step, ds, total_cnt);
                cmd = DRV_IOW(DsErmResrcMonGroupQueueMax_t, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
            }
        }
        else if (SYS_IS_CPU_QUEUE(queue_id))
        {
            cmd = DRV_IOR(ErmResrcMonDmaCtl_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
            value[0] = GetErmResrcMonDmaCtl(V, resrcMonDmaEn_f, ds);
            value[1] = GetErmResrcMonDmaCtl(V, resrcMonDmaQueId_f, ds);
            value[2] = queue_id - MCHIP_CAP(SYS_CAP_QOS_QUEUE_BASE_EXCP);

            if (value[0] && value[1] == value[2])
            {
                cmd = DRV_IOR(DsErmResrcMonDmaQueueMax_t, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
                SetDsErmResrcMonDmaQueueMax(V, dmaQueCntMax_f, ds, total_cnt);
                cmd = DRV_IOW(DsErmResrcMonDmaQueueMax_t, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
            }
        }
        else
        {
            return CTC_E_INVALID_PARAM;
        }
    }
    return CTC_E_NONE;
}

STATIC int32
_sys_usw_monitor_set_thrd(uint8 lchip, uint8 type, uint8 buffer_type, uint8 index, uint32 thrd, uint16 channel_id)
{
    uint32 cmd = 0;
    uint32 field_val = 0;
    uint32 step = 0;

    if (CTC_MONITOR_BUFFER == type)
    {
        field_val = thrd;
        switch(buffer_type)
        {
            case CTC_MONITOR_BUFFER_PORT:
                if (DRV_FROM_AT(lchip))
                {
                    uint16 sub_chan = 0;
                    uint8 dp_id = 0;
                    uint8 pp_id = 0;

                    /*DP*/
                    sys_usw_port_api_get_sub_chan_by_chan(lchip, 0, channel_id, &sub_chan, &pp_id, &dp_id);
                    if (sub_chan >= MCHIP_CAP(SYS_CAP_PER_DP_PHY_CHANNEL_NUM))
                    {
                        /*check network channel*/
                        return CTC_E_NONE;
                    }
                    cmd = (index==0)?DRV_IOW(DsErmPortMbCfg_t, DsErmPortMbCfg_minThrd_f):DRV_IOW(DsErmPortMbCfg_t, DsErmPortMbCfg_maxThrd_f);
                    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(SYS_PP_BASE(lchip) + pp_id, sub_chan, DRV_CMD_DP_EN(cmd, dp_id), &field_val));
                }
                else
                {
                    cmd = (index==0)?DRV_IOW(DsErmPortMbCfg_t, DsErmPortMbCfg_mbMinThrd_f):DRV_IOW(DsErmPortMbCfg_t, DsErmPortMbCfg_mbMaxThrd_f);
                    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, channel_id, cmd, &field_val));
                }


                p_usw_monitor_master[lchip]->mb_thrd->port_thrd[channel_id][index] = field_val;
                break;

            case CTC_MONITOR_BUFFER_PORT_PRIO_CLASS:
            {
                    uint16 sub_chan = 0;
                    uint8 dp_id = 0;
                    uint8 pp_id = 0;

                    /*DP*/
                    sys_usw_port_api_get_sub_chan_by_chan(lchip, 0, channel_id, &sub_chan, &pp_id, &dp_id);
                    if (sub_chan >= MCHIP_CAP(SYS_CAP_PER_DP_PHY_CHANNEL_NUM))
                    {
                        /*check network channel*/
                        return CTC_E_NONE;
                    }

                if (index > 1)
                {
                    /*level1*/
                    cmd = (index==2)?DRV_IOW(DsErmPortTcMbCfg_t, DsErmPortTcMbCfg_g_1_minThrd_f):DRV_IOW(DsErmPortTcMbCfg_t, DsErmPortTcMbCfg_g_1_maxThrd_f);
                    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(SYS_PP_BASE(lchip) + pp_id, sub_chan, DRV_CMD_DP_EN(cmd, dp_id), &field_val));
                    p_usw_monitor_master[lchip]->mb_thrd->porttc_thrd[channel_id * SYS_MONITOR_PRIO_CLASS_LEVEL_NUM + 1][index - 2] = field_val;
                }
                else
                {
                    /*level0*/
                    cmd = (index==0)?DRV_IOW(DsErmPortTcMbCfg_t, DsErmPortTcMbCfg_g_0_minThrd_f):DRV_IOW(DsErmPortTcMbCfg_t, DsErmPortTcMbCfg_g_0_maxThrd_f);
                    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(SYS_PP_BASE(lchip) + pp_id, sub_chan, DRV_CMD_DP_EN(cmd, dp_id), &field_val));
                    p_usw_monitor_master[lchip]->mb_thrd->porttc_thrd[channel_id * SYS_MONITOR_PRIO_CLASS_LEVEL_NUM][index] = field_val;
                }
            }
                break;

            case CTC_MONITOR_BUFFER_SC:
                step = ErmGlbMbCfg_sc_1_scMbMinThrd_f - ErmGlbMbCfg_sc_0_scMbMinThrd_f;
                cmd = (index==0)?DRV_IOW(ErmGlbMbCfg_t, ErmGlbMbCfg_sc_0_scMbMinThrd_f + step * channel_id):
                                 DRV_IOW(ErmGlbMbCfg_t, ErmGlbMbCfg_sc_0_scMbMaxThrd_f + step * channel_id);
                CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));

                p_usw_monitor_master[lchip]->mb_thrd->sc_thrd[channel_id][index] = field_val;
                break;

            case CTC_MONITOR_BUFFER_C2C:
                cmd = (index==0)?DRV_IOW(ErmGlbMbCfg_t, ErmGlbMbCfg_c2cMbMinThrd_f):DRV_IOW(ErmGlbMbCfg_t, ErmGlbMbCfg_c2cMbMaxThrd_f);
                CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));

                p_usw_monitor_master[lchip]->mb_thrd->c2c_thrd[index] = field_val;
                break;
            case CTC_MONITOR_BUFFER_CONTROL:
                cmd = (index==0)?DRV_IOW(ErmGlbMbCfg_t, ErmGlbMbCfg_criticalMbMinThrd_f):DRV_IOW(ErmGlbMbCfg_t, ErmGlbMbCfg_criticalMbMaxThrd_f);
                CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));

                p_usw_monitor_master[lchip]->mb_thrd->critical_thrd[index] = field_val;
                break;
            case CTC_MONITOR_BUFFER_TOTAL:
                cmd = (index==0)?DRV_IOW(ErmGlbMbCfg_t, ErmGlbMbCfg_totalMbMinThrd_f):DRV_IOW(ErmGlbMbCfg_t, ErmGlbMbCfg_totalMbMaxThrd_f);
                CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));

                p_usw_monitor_master[lchip]->mb_thrd->total_thrd[index] = field_val;
                break;
            default:
                return CTC_E_INVALID_PARAM;
        }
    }
    else
    {
        uint16 threshold = 0;
        uint16 shift = 0;

        sys_usw_common_get_compress_near_division_value(lchip, thrd,
                                MCHIP_CAP(SYS_CAP_MONITOR_DIVISION_WIDE), MCHIP_CAP(SYS_CAP_MONITOR_SHIFT_WIDE), &threshold, &shift, 0);
        field_val = threshold;
        step = DsLatencyMonCtl_array_1_latencyThrdHigh_f - DsLatencyMonCtl_array_0_latencyThrdHigh_f;
        cmd = DRV_IOW(DsLatencyMonCtl_t, DsLatencyMonCtl_array_0_latencyThrdHigh_f + index*step);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));

        step = DsLatencyMonCtl_array_1_latencyThrdShift_f - DsLatencyMonCtl_array_0_latencyThrdShift_f;
        field_val = shift;
        cmd = DRV_IOW(DsLatencyMonCtl_t, DsLatencyMonCtl_array_0_latencyThrdShift_f + index*step);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
    }

    return CTC_E_NONE;

}


STATIC int32
_sys_usw_monitor_get_thrd(uint8 lchip, uint8 type, uint8 buffer_type,uint8 index, uint32* thrd, uint16 channel)
{
    uint32 cmd = 0;
    uint32 field_val = 0;

    if (CTC_MONITOR_BUFFER == type)
    {
        /*index=0:get min thrd; index=1:get max thrd*/
        switch(buffer_type)
        {
            case CTC_MONITOR_BUFFER_PORT:
                field_val = p_usw_monitor_master[lchip]->mb_thrd->port_thrd[channel][index];
                break;

            case CTC_MONITOR_BUFFER_PORT_PRIO_CLASS:
                if (index > 1)
                {
                    field_val = p_usw_monitor_master[lchip]->mb_thrd->porttc_thrd[channel * SYS_MONITOR_PRIO_CLASS_LEVEL_NUM + 1][index - 2];
                }
                else
                {
                    field_val = p_usw_monitor_master[lchip]->mb_thrd->porttc_thrd[channel * SYS_MONITOR_PRIO_CLASS_LEVEL_NUM][index];
                }
                break;

            case CTC_MONITOR_BUFFER_SC:
                field_val = p_usw_monitor_master[lchip]->mb_thrd->sc_thrd[channel][index];
                break;

            case CTC_MONITOR_BUFFER_C2C:
                field_val = p_usw_monitor_master[lchip]->mb_thrd->c2c_thrd[index];
                break;
            case CTC_MONITOR_BUFFER_CONTROL:
                field_val = p_usw_monitor_master[lchip]->mb_thrd->critical_thrd[index];
                break;
            case CTC_MONITOR_BUFFER_TOTAL:
                field_val = p_usw_monitor_master[lchip]->mb_thrd->total_thrd[index];
                break;
            default:
                return CTC_E_INVALID_PARAM;
        }
        *thrd = field_val;
    }
    else if(CTC_MONITOR_LATENCY == type)
    {
        uint32 threshold = 0;
        uint32 shift = 0;
        uint32 step = 0;

        step = DsLatencyMonCtl_array_1_latencyThrdHigh_f - DsLatencyMonCtl_array_0_latencyThrdHigh_f;
        cmd = DRV_IOR(DsLatencyMonCtl_t, DsLatencyMonCtl_array_0_latencyThrdHigh_f + index*step);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &threshold));
        step = DsLatencyMonCtl_array_1_latencyThrdShift_f - DsLatencyMonCtl_array_0_latencyThrdShift_f;
        cmd = DRV_IOR(DsLatencyMonCtl_t, DsLatencyMonCtl_array_0_latencyThrdShift_f + index*step);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &shift));
        *thrd = (threshold << shift);
    }
    else
    {
        *thrd = p_usw_monitor_master[lchip]->mburst_thrd[index];
    }

    return CTC_E_NONE;

}


STATIC int32
_sys_usw_monitor_mapping_log_thrd2shift(uint32 data, uint32* value)
{
    *value = 0;
    while( data > 1 )
    {
        data = data >> 1;
        *value = *value + 1;
    }

    return 0;
}


#ifndef EMULATION_ENV
STATIC int32
_sys_usw_monitor_get_timer_cfg_buffer(uint8 lchip, uint32 scan_timer, uint64* p_scan_interval,  uint32* p_max_ptr)
{
    uint32 core_freq = 0;
    uint32 min_scan_ptr = 0;
    uint32 core_div = DRV_FROM_AT(lchip) ? 50000 : 20000;

    core_freq = sys_usw_get_core_freq(lchip, 0) * 1000000 / DOWN_FRE_RATE;
    if (DRV_IS_AT(lchip))
    {
        /*
        when scanPtr[8:4] < 26, do egress queue&portSc scan,
        portIndex = scanPtr[8:4] 
            when scanPtr[0:3] < 11, do queue scan, queueIndex = scanPtr[0:3]
            when scanPtr[0:3] >= 11, do portSc scan, portScIndex = scanPtr[0:3]
        */
        /*
        when scanPtr[8:4] >= 26, do egress port scan,
        scanPtr0 = scanPtr[8:4]-26) << 4) + scanPtr[0:3]
            when scanPtr0 < 26
            portIndexValid = true and portIndex = scanPtr0[4:0] 
        */
        *p_max_ptr = (((MCHIP_CAP(SYS_CAP_PER_DP_CHANNEL_NUM) + 1) << 4) & 0x1F0) + ((MCHIP_CAP(SYS_CAP_PER_DP_CHANNEL_NUM) - (1 << 4) ) & 0xF) + 2;
    }
    else 
    {
        *p_max_ptr = DRV_FROM_TMM(lchip) ? (core_freq / core_div - 1) : 59999;
    }
    
     *p_scan_interval = ((uint64)scan_timer*(core_freq/1000)) / (*p_max_ptr+1-min_scan_ptr) - 1;

    return CTC_E_NONE;
}

STATIC int32
_sys_usw_monitor_get_timer_cfg_latency(uint8 lchip, uint32 scan_timer, uint64* p_scan_interval,  uint32* p_max_ptr)
{
    uint32 core_freq = 0;
    uint32 min_scan_ptr = 0;
    uint32 core_div = DRV_FROM_AT(lchip) ? 50000 : 20000;

    core_freq = sys_usw_get_core_freq(lchip, 0) * 1000000 / DOWN_FRE_RATE;
    *p_max_ptr = DRV_FROM_TMM(lchip) ? (core_freq / core_div - 1) : 59999;
    
    *p_scan_interval = ((uint64)scan_timer*(core_freq/1000)) / (*p_max_ptr+1-min_scan_ptr) - 1;

    return CTC_E_NONE;
}
#endif


int32
sys_usw_monitor_set_timer(uint8 lchip, uint8 monitor_type, uint32 scan_timer)
{
    uint8  pp_id = 0;
    uint8  dp_id = 0; 
    uint8  pp_base = 0;
    uint32 cmd = 0;
    uint32 max_phy_ptr = 0;
    uint32 min_scan_ptr = 0;
    uint32 max_scan_ptr = 0;
    uint64 scan_interval = 0;

    if (monitor_type == CTC_MONITOR_BUFFER)
    {
        /*BufferMonitorTimer*/
#ifdef EMULATION_ENV
        max_scan_ptr = 59999;
        scan_interval = 10;
#else
        _sys_usw_monitor_get_timer_cfg_buffer(lchip, scan_timer, &scan_interval, &max_scan_ptr);
        if (scan_interval > (DRV_FROM_AT(lchip) ? CTC_MAX_UINT32_VALUE : CTC_MAX_UINT16_VALUE))
        {
            return CTC_E_INVALID_PARAM;
        }
#endif
        if(DRV_FROM_AT(lchip))
        {
            ErmResrcStateInformScanCtl_m erm_resrc_state_ctl;
            pp_base = SYS_PP_BASE(lchip);

            if (MCHIP_MON(lchip)->buf_sync_interval)
            {
                /*Set DMA time*/
                CTC_ERROR_RETURN(MCHIP_MON(lchip)->buf_sync_interval(lchip, 1, &scan_timer));
            }
            for (pp_id = pp_base; pp_id < (SYS_PP_NUM(lchip) + pp_base); pp_id++)
            {
                for (dp_id = 0; dp_id < MCHIP_CAP(SYS_CAP_DP_MAX_NUM); dp_id++)
                {                        
                    cmd = DRV_IOR(ErmResrcStateInformScanCtl_t, DRV_ENTRY_FLAG);
                    CTC_ERROR_RETURN(DRV_IOCTL(pp_id, 0, DRV_CMD_DP_EN(cmd, dp_id), &erm_resrc_state_ctl));
                    SetErmResrcStateInformScanCtl(V, resrcStateInformScanMax_f, &erm_resrc_state_ctl, max_scan_ptr-2);/*2 is adjust for precision*/
                    SetErmResrcStateInformScanCtl(V, resrcStateInformScanInterval_f, &erm_resrc_state_ctl, scan_interval);
                    cmd = DRV_IOW(ErmResrcStateInformScanCtl_t, DRV_ENTRY_FLAG);
                    CTC_ERROR_RETURN(DRV_IOCTL(pp_id, 0, DRV_CMD_DP_EN(cmd, dp_id), &erm_resrc_state_ctl));
                }
            }
        }
        else
        {
            ErmResrcMonScanCtl_m resrc_mon_scan_ctl;
            IrmResrcMonScanCtl_m irm_resrc_mon_scan_ctl;
            sal_memset(&resrc_mon_scan_ctl, 0, sizeof(resrc_mon_scan_ctl));
            sal_memset(&irm_resrc_mon_scan_ctl, 0, sizeof(irm_resrc_mon_scan_ctl));
            cmd = DRV_IOR(ErmResrcMonScanCtl_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &resrc_mon_scan_ctl));
            SetErmResrcMonScanCtl(V, resrcMonScanPtrMax_f , &resrc_mon_scan_ctl, max_scan_ptr-2);/*2 is adjust for precision*/
            SetErmResrcMonScanCtl(V, resrcMonScanInterval_f       , &resrc_mon_scan_ctl,  scan_interval);
            cmd = DRV_IOW(ErmResrcMonScanCtl_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &resrc_mon_scan_ctl));

            for(dp_id = 0; dp_id < MCHIP_CAP(SYS_CAP_DP_MAX_NUM); dp_id++)
            {
            cmd = DRV_IOR(IrmResrcMonScanCtl_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, dp_id, cmd, &irm_resrc_mon_scan_ctl));
            SetIrmResrcMonScanCtl(V, resrcMonScanPtrMax_f , &irm_resrc_mon_scan_ctl, max_scan_ptr-2);/*2 is adjust for precision*/
            SetIrmResrcMonScanCtl(V, resrcMonScanInterval_f       , &irm_resrc_mon_scan_ctl,  scan_interval);
            cmd = DRV_IOW(IrmResrcMonScanCtl_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, dp_id, cmd, &irm_resrc_mon_scan_ctl));
            }
        }
    }
    else
    {
        /*LatencyMonitorTimer*/
        LatencyMonScanCtl_m latency_mon_scan_ctl;
        sal_memset(&latency_mon_scan_ctl, 0, sizeof(latency_mon_scan_ctl));
        max_phy_ptr = MCHIP_CAP(SYS_CAP_MONITOR_MAX_CHAN_PER_SLICE) - 1;
#ifdef EMULATION_ENV
        max_scan_ptr = 257;
        scan_interval = 10;
#else
        _sys_usw_monitor_get_timer_cfg_latency(lchip, scan_timer, &scan_interval, &max_scan_ptr);
        if(scan_interval > CTC_MAX_UINT16_VALUE)
        {
            return CTC_E_INVALID_PARAM;
        }
#endif
        cmd = DRV_IOR(LatencyMonScanCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &latency_mon_scan_ctl));
        SetLatencyMonScanCtl(V, scanMaxPhyPtr_f , &latency_mon_scan_ctl, max_phy_ptr);
        SetLatencyMonScanCtl(V, scanMinPtr_f     , &latency_mon_scan_ctl, min_scan_ptr);
        SetLatencyMonScanCtl(V, scanMaxPtr_f , &latency_mon_scan_ctl, max_scan_ptr-1);/*1 is adjust for precision*/
        SetLatencyMonScanCtl(V, scanInterval_f        , &latency_mon_scan_ctl, scan_interval);
        cmd = DRV_IOW(LatencyMonScanCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &latency_mon_scan_ctl));
    }
    return CTC_E_NONE;
}


STATIC int32
_sys_usw_monitor_get_scan_timer(uint8 lchip, uint32 *scan_timer, uint32 scan_interval, uint32 max_ptr)
{
    uint32 delta = 1;
    uint32 core_freq = 0;
    uint32 min_scan_ptr = 0;
    uint32 value = 0;
    core_freq = sys_usw_get_core_freq(lchip, 0) * 1000000 / DOWN_FRE_RATE;
    value = (max_ptr - min_scan_ptr + 1)*(scan_interval + 1)*delta / (core_freq/1000);
    *scan_timer = value;

    return CTC_E_NONE;
}

int32
_sys_usw_monitor_get_mburst_level(uint8 lchip, uint8 *level, uint64 thrd)
{
    uint8 index = 0;
    for(index = 0; index <= MCHIP_CAP(SYS_CAP_MONITOR_LATENCY_MAX_LEVEL); index ++)
    {
        if(thrd < p_usw_monitor_master[lchip]->mburst_thrd[index] && index != 0)
        {
            *level = index - 1;
            break;
        }
        else if(thrd < p_usw_monitor_master[lchip]->mburst_thrd[index] && index == 0)
        {
            *level = 0xff;
            break;
        }
        else
        {
            *level = MCHIP_CAP(SYS_CAP_MONITOR_LATENCY_MAX_LEVEL);
        }
    }

    return CTC_E_NONE;
}
#if 0
STATIC int32
_sys_usw_monitor_thrd_check(uint8 lchip, uint8 level, uint32 thrd,uint8 type)
{
    uint32 threshold_min = 0;
    uint32 threshold_max = 0;
    if(level == 0)
    {
        if(type == CTC_MONITOR_GLB_CONFIG_LATENCY_THRD)
        {
            CTC_ERROR_RETURN(_sys_usw_monitor_get_thrd(lchip, CTC_MONITOR_LATENCY, 0,level+1, &threshold_max, 0));
        }
        else if(type == CTC_MONITOR_GLB_CONFIG_MBURST_THRD)
        {
            threshold_max = p_usw_monitor_master[lchip]->mburst_thrd[level + 1];
        }
        CTC_MAX_VALUE_CHECK(thrd, threshold_max);
    }
    else if(level == MCHIP_CAP(SYS_CAP_MONITOR_LATENCY_MAX_LEVEL))
    {
        if(type == CTC_MONITOR_GLB_CONFIG_LATENCY_THRD)
        {
            CTC_ERROR_RETURN(_sys_usw_monitor_get_thrd(lchip, CTC_MONITOR_LATENCY, 0,level-1, &threshold_min, 0));
        }
        else if(type == CTC_MONITOR_GLB_CONFIG_MBURST_THRD)
        {
            threshold_min = p_usw_monitor_master[lchip]->mburst_thrd[level - 1];
        }
        CTC_MIN_VALUE_CHECK(thrd, threshold_min);
    }
    else
    {
        if(type == CTC_MONITOR_GLB_CONFIG_LATENCY_THRD)
        {
            CTC_ERROR_RETURN(_sys_usw_monitor_get_thrd(lchip, CTC_MONITOR_LATENCY, 0,level-1, &threshold_min, 0));
            CTC_ERROR_RETURN(_sys_usw_monitor_get_thrd(lchip, CTC_MONITOR_LATENCY, 0,level+1, &threshold_max, 0));
        }
        else if(type == CTC_MONITOR_GLB_CONFIG_MBURST_THRD)
        {
            CTC_ERROR_RETURN(_sys_usw_monitor_get_thrd(lchip, CTC_MONITOR_MSG_MBURST_STATS, 0,level-1, &threshold_min, 0));
            CTC_ERROR_RETURN(_sys_usw_monitor_get_thrd(lchip, CTC_MONITOR_MSG_MBURST_STATS, 0,level+1, &threshold_max, 0));
        }
        CTC_VALUE_RANGE_CHECK(thrd, threshold_min, threshold_max);
    }
    return CTC_E_NONE;
}
#endif
int32
sys_usw_monitor_get_timer(uint8 lchip, uint8 monitor_type, uint32 *scan_timer)
{
    uint32 cmd = 0;
    ErmResrcMonScanCtl_m resrc_mon_scan_ctl;
    LatencyMonScanCtl_m latency_mon_scan_ctl;
    uint32 max_scan_ptr = 0;
    uint32 scan_interval = 0;

    sal_memset(&resrc_mon_scan_ctl, 0, sizeof(resrc_mon_scan_ctl));
    sal_memset(&latency_mon_scan_ctl, 0, sizeof(latency_mon_scan_ctl));
    if (monitor_type == CTC_MONITOR_BUFFER)
    {
        if (DRV_FROM_AT(lchip) && MCHIP_MON(lchip)->buf_sync_interval)
        {
            /*Get DMA time*/
            return MCHIP_MON(lchip)->buf_sync_interval(lchip, 0, scan_timer);

        }

        /*BufferMonitorTimer*/
        sal_memset(&resrc_mon_scan_ctl, 0, sizeof(resrc_mon_scan_ctl));
        cmd = DRV_IOR(ErmResrcMonScanCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &resrc_mon_scan_ctl));
        max_scan_ptr = GetErmResrcMonScanCtl(V, resrcMonScanPtrMax_f , &resrc_mon_scan_ctl);
        scan_interval = GetErmResrcMonScanCtl(V, resrcMonScanInterval_f , &resrc_mon_scan_ctl);
        max_scan_ptr += 2; /*adjust for precision*/
        _sys_usw_monitor_get_scan_timer(lchip, scan_timer, scan_interval, max_scan_ptr);


    }
    else
    {
        /*LatencyMonitorTimer*/
        sal_memset(&latency_mon_scan_ctl, 0, sizeof(latency_mon_scan_ctl));
        cmd = DRV_IOR(LatencyMonScanCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &latency_mon_scan_ctl));
        max_scan_ptr = GetLatencyMonScanCtl(V, scanMaxPtr_f , &latency_mon_scan_ctl);
        max_scan_ptr += 1; /*adjust for precision*/
        scan_interval = GetLatencyMonScanCtl(V, scanInterval_f        , &latency_mon_scan_ctl);
        _sys_usw_monitor_get_scan_timer(lchip, scan_timer, scan_interval, max_scan_ptr);
    }
    return CTC_E_NONE;

}
#if 0
uint8
_sys_usw_monitor_channel_convert(uint8 lchip, uint8 chan_id)
{
    uint32 cmd = 0;
    uint8 temp = 0;
    uint32 max_scan_ptr = 0;
    uint32 scan_ptr = 0;
    QMgrEnqCtl_m q_mgr_enq_ctl;

    /*slice 0 do not need convert */
    if (chan_id < MCHIP_CAP(SYS_CAP_MONITOR_MAX_CHAN_PER_SLICE))
    {
        return chan_id;
    }

    /*Get scan max buf ptr */
    cmd = DRV_IOR(QMgrEnqCtl_t, DRV_ENTRY_FLAG);
    (DRV_IOCTL(lchip, 0, cmd, &q_mgr_enq_ctl));
    max_scan_ptr = GetQMgrEnqCtl(V, maxBufScanPtr_f , &q_mgr_enq_ctl);

    scan_ptr = max_scan_ptr/2 + (chan_id - MCHIP_CAP(SYS_CAP_MONITOR_MAX_CHAN_PER_SLICE));
    scan_ptr = scan_ptr & 0x3F;
    temp = MCHIP_CAP(SYS_CAP_MONITOR_MAX_CHAN_PER_SLICE) + scan_ptr;

    return temp;
}
#endif

STATIC int32
_sys_usw_monitor_check_inform(uint8 lchip, uint8 buffer_type)
{
    uint16 loop      = 0;
    uint32 cmd       = 0;
    uint32 entry_num = 0;
    uint32 value_tmp = 0;

    switch (buffer_type)
    {
    case CTC_MONITOR_BUFFER_PORT:
    {
        /* check fast ecn & port tc mb enable */
        PreBufferRetrieveCtl_m br_ctl;
        cmd = DRV_IOR(PreBufferRetrieveCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &br_ctl));    
        value_tmp = GetPreBufferRetrieveCtl(V, mbTcMode_f, &br_ctl);
        if(value_tmp)
        {
            return CTC_E_PARAM_CONFLICT;
        }
        break;
    }
    case CTC_MONITOR_BUFFER_PORT_PRIO_CLASS:
    {
        uint8  dp_id      = 0;
        uint8  dp_chan    = 0;
        uint8  lchip_tmp  = 0;
        DsDestChannel_m  dest_chan;
        DsErmPortMbCfg_m erm_port_mb;

        /* 1. check port tc mb enable */
        for (dp_id = 0; dp_id < SYS_PP_NUM(lchip) * MCHIP_CAP(SYS_CAP_DP_MAX_NUM); dp_id++)
        {
            lchip_tmp = SYS_PP_BASE(lchip) + dp_id / MCHIP_CAP(SYS_CAP_DP_MAX_NUM);
            for (dp_chan = 0; dp_chan < MCHIP_CAP(SYS_CAP_PER_DP_CHANNEL_NUM); dp_chan++)
            {
                cmd = DRV_IOR(DsErmPortMbCfg_t, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(lchip_tmp, dp_chan, DRV_CMD_DP_EN(cmd, dp_id % MCHIP_CAP(SYS_CAP_DP_MAX_NUM)), &erm_port_mb));
                value_tmp = GetDsErmPortMbCfg(V, mbInformEn_f, &erm_port_mb);
                if (value_tmp)
                {
                    return CTC_E_PARAM_CONFLICT;
                }
            }
        }

        /* 2. check fast ecn enable */
        sys_usw_ftm_query_table_entry_num(lchip, DsDestChannel_t, &entry_num);
        for (loop = 0; loop < entry_num; loop++)
        {
            cmd = DRV_IOR(DsDestChannel_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, loop, cmd, &dest_chan));
            value_tmp = GetDsDestChannel(V, microburstAsCongestion_f, &dest_chan);
            if(value_tmp)
            {
                return CTC_E_PARAM_CONFLICT;
            }
        }
        break;
    }
    default:
        return CTC_E_INVALID_PARAM;
    }

    return CTC_E_NONE;
}

int32
sys_usw_monitor_set_buffer_inform(uint8 lchip, ctc_monitor_config_t *p_cfg)
{
    uint32 cmd = 0;
    uint16 loop = 0;
    uint16 lport = 0;
    uint32 gport = 0;
    uint32 channel_id = 0;
    uint32 field_val = 0;
    uint32 value_tmp = 0;
    uint32 sub_chan = 0;
    uint32 pp_id = 0;
    uint32 dp_id = 0;
    ErmMiscCtlUc_m erm_misc_ctl_uc;

    field_val = p_cfg->value?1:0;
    if (!DRV_FROM_AT(lchip))
    {
        ErmMiscCtl_m erm_misc_ctl;
        cmd = DRV_IOR(ErmMiscCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &erm_misc_ctl));
        SetErmMiscCtl(V, microBurstInformEn_f, &erm_misc_ctl, field_val);
        SetErmMiscCtl(V, c2cMicroBurstInformEn_f, &erm_misc_ctl, field_val);
        SetErmMiscCtl(V, criticalMicroBurstInformEn_f, &erm_misc_ctl, field_val);
        SetErmMiscCtl(V, totalMicroBurstInformEn_f, &erm_misc_ctl, field_val);
        SetErmMiscCtl(V, scMicroBurstInformEn_f, &erm_misc_ctl, p_cfg->value ? 15 : 0);
        cmd = DRV_IOW(ErmMiscCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &erm_misc_ctl));
        return CTC_E_NONE;
    }
    if (CTC_MONITOR_BUFFER_PORT == p_cfg->buffer_type || CTC_MONITOR_BUFFER_PORT_PRIO_CLASS == p_cfg->buffer_type)
    {
        sys_port_info_t port_info = {0};
        gport = p_cfg->gport;
        SYS_MAP_CTC_GPORT_TO_DRV_LPORT_WITH_CHECK(gport, lchip, lport);
        if (!SYS_GPORT_IS_NETWORK_PORT(gport))
        {
            return CTC_E_INVALID_PORT;
        }
        CTC_ERROR_RETURN(sys_usw_port_api_get_com_info(lchip, lport, CTC_MAP_GPORT_TO_MCHAN_IDX(gport), &port_info));
        sub_chan = port_info.sub_chan_id;
        channel_id = port_info.chan_id;
        pp_id = port_info.pp_id;
        dp_id = port_info.dp_id;
        pp_id += SYS_PP_BASE(lchip);
    }
    cmd = DRV_IOR(ErmMiscCtlUc_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &erm_misc_ctl_uc));
    switch (p_cfg->buffer_type)
    {
        case CTC_MONITOR_BUFFER_PORT:
        {
            DsErmPortMbCfg_m erm_port_mb;

            /*1. check fast ecn & port tc mb enable*/
            CTC_ERROR_RETURN(_sys_usw_monitor_check_inform(lchip, CTC_MONITOR_BUFFER_PORT));

            cmd = DRV_IOR(DsErmPortMbCfg_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(pp_id, sub_chan, DRV_CMD_DP_EN(cmd, dp_id), &erm_port_mb));
            SetDsErmPortMbCfg(V, mbInformEn_f, &erm_port_mb, field_val);
            cmd = DRV_IOW(DsErmPortMbCfg_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(pp_id, sub_chan, DRV_CMD_DP_EN(cmd, dp_id), &erm_port_mb));
        }
            break;
        case CTC_MONITOR_BUFFER_SC:
            field_val = GetErmMiscCtlUc(V, scMicroBurstInformEn_f, &erm_misc_ctl_uc);
            p_cfg->value ? CTC_BIT_SET(field_val, p_cfg->sc) : CTC_BIT_UNSET(field_val, p_cfg->sc);
            SetErmMiscCtlUc(V, scMicroBurstInformEn_f, &erm_misc_ctl_uc,  field_val);
            cmd = DRV_IOW(ErmMiscCtlUc_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &erm_misc_ctl_uc));
            break;
        case CTC_MONITOR_BUFFER_TOTAL:
            SetErmMiscCtlUc(V, totalMicroBurstInformEn_f, &erm_misc_ctl_uc, field_val);
            cmd = DRV_IOW(ErmMiscCtlUc_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &erm_misc_ctl_uc));
            break;
        case CTC_MONITOR_BUFFER_C2C:
            SetErmMiscCtlUc(V, c2cMicroBurstInformEn_f, &erm_misc_ctl_uc, field_val);
            cmd = DRV_IOW(ErmMiscCtlUc_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &erm_misc_ctl_uc));
            break;
        case CTC_MONITOR_BUFFER_CONTROL:
            SetErmMiscCtlUc(V, criticalMicroBurstInformEn_f, &erm_misc_ctl_uc, field_val);
            cmd = DRV_IOW(ErmMiscCtlUc_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &erm_misc_ctl_uc));
            break;
        case CTC_MONITOR_BUFFER_PORT_PRIO_CLASS:
        {
            uint32 prio_class_bmp = 0;
            int32 count = 0;
            int32 count2 = 0;
            uint8 index = 0;
            uint8 dp_chan = 0;
            uint8 lchip_tmp = 0;
            uint8 level_bmp[2] = {0};
            uint8 field_val1 = 0;
            uint8 step = 0;
            uint8 i = 0;
            DsErmPortTcMbCfg_m erm_porttc_mb;
            ErmMbCtl_m erm_mb_ctl;
            PreBufferRetrieveCtl_m br_ctl;
             
            CTC_MAX_VALUE_CHECK(p_cfg->level, 1);

            /*1. check port mb & fast ecn enable*/
            CTC_ERROR_RETURN(_sys_usw_monitor_check_inform(lchip, CTC_MONITOR_BUFFER_PORT_PRIO_CLASS));

            /*get global 2 priority class*/
            step = DsErmPortTcMbCfg_tc_1_mbSel_f - DsErmPortTcMbCfg_tc_0_mbSel_f;
            for (index = 0; index < SYS_PP_NUM(lchip) * MCHIP_CAP(SYS_CAP_DP_MAX_NUM); index++)
            {
                lchip_tmp = SYS_PP_BASE(lchip) + index / MCHIP_CAP(SYS_CAP_DP_MAX_NUM);
                for (dp_chan = 0; dp_chan < MCHIP_CAP(SYS_CAP_PER_DP_CHANNEL_NUM); dp_chan++)
                {
                    cmd = DRV_IOR(DsErmPortTcMbCfg_t, DRV_ENTRY_FLAG);
                    CTC_ERROR_RETURN(DRV_IOCTL(lchip_tmp, dp_chan, DRV_CMD_DP_EN(cmd, index % MCHIP_CAP(SYS_CAP_DP_MAX_NUM)), &erm_porttc_mb));
                    for(i = 0; i < SYS_MONITOR_PRIO_CLASS_NUM_MAX; i++)
                    {
                        field_val1 = GetDsErmPortTcMbCfg(V, tc_0_mbSel_f + step * i, &erm_porttc_mb);
                        if(field_val1 != 3)
                        {
                            CTC_BIT_SET(prio_class_bmp, i);
                        }
                    }
                }
            }

            CTC_BMP_COUNT(prio_class_bmp, count, 0, 8);
            CTC_MAX_VALUE_CHECK(count, 2);
            if(count == 0 && field_val == 0)
            {
                return CTC_E_NONE;
            }
            else if(count == 2 && !CTC_IS_BIT_SET(prio_class_bmp, p_cfg->sc))
            {
                return CTC_E_PARAM_CONFLICT;
            }

            cmd = DRV_IOR(DsErmPortTcMbCfg_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(pp_id, sub_chan , DRV_CMD_DP_EN(cmd, dp_id), &erm_porttc_mb));
            value_tmp = DsErmPortTcMbCfg_tc_1_mbSel_f - DsErmPortTcMbCfg_tc_0_mbSel_f;
            field_val ? SetDsErmPortTcMbCfg(V, tc_0_mbSel_f + p_cfg->sc * value_tmp, &erm_porttc_mb, p_cfg->level)
                      : SetDsErmPortTcMbCfg(V, tc_0_mbSel_f + p_cfg->sc * value_tmp, &erm_porttc_mb, 3); /*3 means disable*/
            for(loop = 0; loop < SYS_MONITOR_PRIO_CLASS_NUM_MAX; loop++)
            {
                field_val1 = GetDsErmPortTcMbCfg(V, tc_0_mbSel_f + loop * value_tmp, &erm_porttc_mb);
                if(field_val1 == 0)
                {
                    CTC_BIT_SET(level_bmp[0], loop);
                }
                else if(field_val1 == 1)
                {
                    CTC_BIT_SET(level_bmp[1], loop);
                }
            }
            SetDsErmPortTcMbCfg(V, g_0_mbInformEn_f, &erm_porttc_mb, level_bmp[0] ? 1 : 0);
            SetDsErmPortTcMbCfg(V, g_1_mbInformEn_f, &erm_porttc_mb, level_bmp[1] ? 1 : 0);
            cmd = DRV_IOW(DsErmPortTcMbCfg_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(pp_id, sub_chan, DRV_CMD_DP_EN(cmd, dp_id), &erm_porttc_mb));
    
            p_cfg->level ? CTC_BMP_SET(p_usw_monitor_master[lchip]->mb_thrd->porttc_lvl_bmp, channel_id * SYS_MONITOR_PRIO_CLASS_NUM + p_cfg->sc)
                         : CTC_BMP_UNSET(p_usw_monitor_master[lchip]->mb_thrd->porttc_lvl_bmp, channel_id * SYS_MONITOR_PRIO_CLASS_NUM + p_cfg->sc);



            prio_class_bmp = 0;
            step = DsErmPortTcMbCfg_tc_1_mbSel_f - DsErmPortTcMbCfg_tc_0_mbSel_f;
            for (index = 0; index < SYS_PP_NUM(lchip) * MCHIP_CAP(SYS_CAP_DP_MAX_NUM); index++)
            {
                lchip_tmp = SYS_PP_BASE(lchip) + index / MCHIP_CAP(SYS_CAP_DP_MAX_NUM);
                for (dp_chan = 0; dp_chan < MCHIP_CAP(SYS_CAP_PER_DP_CHANNEL_NUM); dp_chan++)
                {
                    cmd = DRV_IOR(DsErmPortTcMbCfg_t, DRV_ENTRY_FLAG);
                    CTC_ERROR_RETURN(DRV_IOCTL(lchip_tmp, dp_chan, DRV_CMD_DP_EN(cmd, index % MCHIP_CAP(SYS_CAP_DP_MAX_NUM)), &erm_porttc_mb));
                    for(i = 0; i < SYS_MONITOR_PRIO_CLASS_NUM_MAX; i++)
                    {
                        field_val1 = GetDsErmPortTcMbCfg(V, tc_0_mbSel_f + step * i, &erm_porttc_mb);
                        if(field_val1 != 3)
                        {
                            CTC_BIT_SET(prio_class_bmp, i);
                        }
                    }
                }
            }
            
            CTC_BMP_COUNT(prio_class_bmp, count2, 0, 8);
            if (count2 == count)
            {
                return CTC_E_NONE;
            }
                    
            field_val1 = 0;
            level_bmp[0] = 0;
            level_bmp[1] = 0;
            for (i = 0; i < SYS_MONITOR_PRIO_CLASS_NUM_MAX; i++)
            {
                if (!CTC_IS_BIT_SET(prio_class_bmp, i) || field_val1 >= 2)
                {
                    continue;
                }
                level_bmp[field_val1++] = i;        
            }
            cmd = DRV_IOR(ErmMbCtl_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &erm_mb_ctl));
            SetErmMbCtl(V, mbTcMode_f, &erm_mb_ctl, count2 ? 1 : 0);
            SetErmMbCtl(V, g_0_selTc_f, &erm_mb_ctl, level_bmp[0]);
            SetErmMbCtl(V, g_1_selTc_f, &erm_mb_ctl, level_bmp[1]);
            cmd = DRV_IOW(ErmMbCtl_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &erm_mb_ctl)); 

            cmd = DRV_IOR(PreBufferRetrieveCtl_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &br_ctl));
            SetPreBufferRetrieveCtl(V, mbTcMode_f, &br_ctl, count2 ? 1 : 0);
            field_val1 = GetPreBufferRetrieveCtl(V, microburstMode_f, &br_ctl);
            if (count2 == 0)
            {
                if (field_val1 == SYS_MONITOR_LOG_MODE_VICTIM_PORT_TC)
                {
                    field_val1 = SYS_MONITOR_LOG_MODE_VICTIM_PORT;
                }
                else if (field_val1 == SYS_MONITOR_LOG_MODE_ALL_PORT_TC)
                {
                    field_val1 = SYS_MONITOR_LOG_MODE_ALL_PORT;
                }
            } 
            else
            {
                if (field_val1 == SYS_MONITOR_LOG_MODE_VICTIM_PORT)
                {
                    field_val1 = SYS_MONITOR_LOG_MODE_VICTIM_PORT_TC;
                }
                else if (field_val1 == SYS_MONITOR_LOG_MODE_ALL_PORT)
                {
                    field_val1 = SYS_MONITOR_LOG_MODE_ALL_PORT_TC;
                }
            }
            SetPreBufferRetrieveCtl(V, microburstMode_f, &br_ctl, field_val1);
            SetPreBufferRetrieveCtl(V, g_0_selTc_f, &br_ctl, level_bmp[0]); 
            SetPreBufferRetrieveCtl(V, g_1_selTc_f, &br_ctl, level_bmp[1]); 
            cmd = DRV_IOW(PreBufferRetrieveCtl_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &br_ctl));

        }
            break;
    
        default:
            return CTC_E_NOT_SUPPORT;
    }
    return CTC_E_NONE;
}

int32
sys_usw_monitor_get_buffer_inform(uint8 lchip, ctc_monitor_config_t *p_cfg)
{
    int32  ret = 0;
    uint32 cmd = 0;
    uint16 lport = 0;
    uint32 gport = 0;
    uint32 field_val = 0;
    uint32 value_tmp = 0;
    uint32 sub_chan = 0;
    uint32 pp_id = 0;
    uint32 dp_id = 0;
    ErmMiscCtlUc_m erm_misc_ctl_uc;

    if (!DRV_FROM_AT(lchip))
    {
        cmd = DRV_IOR(ErmMiscCtl_t, ErmMiscCtl_microBurstInformEn_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        p_cfg->value = field_val;
        return CTC_E_NONE;
    }
    if (CTC_MONITOR_BUFFER_PORT == p_cfg->buffer_type || CTC_MONITOR_BUFFER_PORT_PRIO_CLASS == p_cfg->buffer_type)
    {
        sys_port_info_t port_info = {0};
        gport = p_cfg->gport;
        SYS_MAP_CTC_GPORT_TO_DRV_LPORT_WITH_CHECK(gport, lchip, lport);
        if (!SYS_GPORT_IS_NETWORK_PORT(gport))
        {
            return CTC_E_INVALID_PORT;
        }
        CTC_ERROR_RETURN(sys_usw_port_api_get_com_info(lchip, lport, CTC_MAP_GPORT_TO_MCHAN_IDX(gport), &port_info));
        sub_chan = port_info.sub_chan_id;
        pp_id = port_info.pp_id;
        dp_id = port_info.dp_id;
        pp_id += SYS_PP_BASE(lchip);
    }
    cmd = DRV_IOR(ErmMiscCtlUc_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &erm_misc_ctl_uc));
    switch (p_cfg->buffer_type)
    {
        case CTC_MONITOR_BUFFER_PORT:
        {
            DsErmPortMbCfg_m erm_port_mb;

            ret = _sys_usw_monitor_check_inform(lchip, CTC_MONITOR_BUFFER_PORT);

            cmd = DRV_IOR(DsErmPortMbCfg_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(pp_id, sub_chan, DRV_CMD_DP_EN(cmd, dp_id), &erm_port_mb));
            field_val = (ret != CTC_E_NONE) ? 0 : GetDsErmPortMbCfg(V, mbInformEn_f, &erm_port_mb);
        }
            break;
        case CTC_MONITOR_BUFFER_SC:
            field_val = GetErmMiscCtlUc(V, scMicroBurstInformEn_f, &erm_misc_ctl_uc);
            field_val = CTC_IS_BIT_SET(field_val, p_cfg->sc);
            break;
        case CTC_MONITOR_BUFFER_TOTAL:
            field_val = GetErmMiscCtlUc(V, totalMicroBurstInformEn_f, &erm_misc_ctl_uc);
            break;
        case CTC_MONITOR_BUFFER_C2C:
            field_val = GetErmMiscCtlUc(V, c2cMicroBurstInformEn_f, &erm_misc_ctl_uc);
            break;
        case CTC_MONITOR_BUFFER_CONTROL:
            field_val = GetErmMiscCtlUc(V, criticalMicroBurstInformEn_f, &erm_misc_ctl_uc);
            break;
        case CTC_MONITOR_BUFFER_PORT_PRIO_CLASS:
        {
            DsErmPortTcMbCfg_m erm_porttc_mb;

            ret = _sys_usw_monitor_check_inform(lchip, CTC_MONITOR_BUFFER_PORT_PRIO_CLASS);

            cmd = DRV_IOR(DsErmPortTcMbCfg_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(pp_id, sub_chan, DRV_CMD_DP_EN(cmd, dp_id), &erm_porttc_mb));
            value_tmp = DsErmPortTcMbCfg_tc_1_mbSel_f - DsErmPortTcMbCfg_tc_0_mbSel_f;
            p_cfg->level = GetDsErmPortTcMbCfg(V, tc_0_mbSel_f + p_cfg->sc * value_tmp, &erm_porttc_mb);
            field_val = ((p_cfg->level > 1) || (ret != CTC_E_NONE)) ? 0 : 1;
        }
            break;
    
        default:
            return CTC_E_NOT_SUPPORT;
    }

    p_cfg->value = field_val;
    return CTC_E_NONE;

}

int32
sys_usw_monitor_set_buffer_scan(uint8 lchip, uint8 tbl_idx, uint32 channel_id, ctc_monitor_config_t *p_cfg)
{
    uint32 cmd = 0;
    uint32 field_val = 0;
    uint32 value[SYS_CHAN_BITMAP_IN_WORD];
    ds_t ds;

    if (MCHIP_MON(lchip)->buffer_scan)
    {
        return MCHIP_MON(lchip)->buffer_scan(lchip, 1, p_cfg);
    }
    if (DRV_IS_TMG(lchip) && (CTC_MONITOR_BUFFER_PORT_SC == p_cfg->buffer_type) && (CTC_INGRESS == p_cfg->dir))
    {
        return CTC_E_NOT_SUPPORT;
    }

    /* ERM scan */
    field_val = p_cfg->value?1:0;
    cmd = p_cfg->dir ? DRV_IOR(ErmResrcMonScanCtl_t, DRV_ENTRY_FLAG): DRV_IOR(IrmResrcMonScanCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, tbl_idx, cmd, ds));
    switch(p_cfg->buffer_type)
    {
    case CTC_MONITOR_BUFFER_PORT:
        if(p_cfg->dir == CTC_EGRESS)
        {
            GetErmResrcMonScanCtl(A, resrcMonScanPushChannelEn_f, ds, value);
            p_cfg->value ? CTC_BIT_SET(value[channel_id >> 5], channel_id&0x1F): CTC_BIT_UNSET(value[channel_id >> 5], channel_id&0x1F);
            SetErmResrcMonScanCtl(A, resrcMonScanPushChannelEn_f, ds, value);
        }
        else
        {
            channel_id = channel_id % MCHIP_CAP(SYS_CAP_PER_DP_CHANNEL_NUM);
            GetIrmResrcMonScanCtl(A, resrcMonScanPushChannelEn_f, ds, value);
            p_cfg->value ? CTC_BIT_SET(value[channel_id >> 5], channel_id&0x1F) : CTC_BIT_UNSET(value[channel_id >> 5], channel_id&0x1F);
            SetIrmResrcMonScanCtl(A, resrcMonScanPushChannelEn_f, ds, value);
    
        }
        break;
    case CTC_MONITOR_BUFFER_PORT_SC:
        if(p_cfg->dir == CTC_EGRESS)
        {
            GetErmResrcMonScanCtl(A, resrcMonScanPushChannelScEn_f, ds, value);
            p_cfg->value ? CTC_BIT_SET(value[channel_id >> 5], channel_id&0x1F) : CTC_BIT_UNSET(value[channel_id >> 5], channel_id&0x1F);
            SetErmResrcMonScanCtl(A, resrcMonScanPushChannelScEn_f, ds, value);
        }
        else
        {
            channel_id = channel_id % MCHIP_CAP(SYS_CAP_PER_DP_CHANNEL_NUM);
            GetIrmResrcMonScanCtl(A, resrcMonScanPushChannelScEn_f, ds, value);
            p_cfg->value ? CTC_BIT_SET(value[channel_id >> 5], channel_id&0x1F) : CTC_BIT_UNSET(value[channel_id >> 5], channel_id&0x1F);
            SetIrmResrcMonScanCtl(A, resrcMonScanPushChannelScEn_f, ds, value);
    
        }
        break;
    case CTC_MONITOR_BUFFER_SC:
        if(p_cfg->dir == CTC_EGRESS)
        {
            SetErmResrcMonScanCtl(V, resrcMonScanPushScEn_f, ds, field_val);
        }
        else
        {
            SetIrmResrcMonScanCtl(V, resrcMonScanPushScEn_f, ds, field_val);
        }
        break;
    case CTC_MONITOR_BUFFER_TOTAL:
        if(p_cfg->dir == CTC_EGRESS)
        {
            SetErmResrcMonScanCtl(V, resrcMonScanPushMiscEn_f, ds, field_val);
        }
        else
        {
            SetIrmResrcMonScanCtl(V, resrcMonScanPushMiscEn_f, ds, field_val);
        }
        break;
    case CTC_MONITOR_BUFFER_QUEUE:
        if(p_cfg->dir == CTC_EGRESS)
        {
            if (DRV_FROM_TMM(lchip))
            {
                SetErmResrcMonScanCtl(V, resrcMonScanPushQueueShadowEn_f, ds, field_val);
            }
            else
            {
                ErmResrcMonPortCtl_m erm_mon_port_ctl;
                cmd = DRV_IOR(ErmResrcMonPortCtl_t, DRV_ENTRY_FLAG);
                CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &erm_mon_port_ctl));
                value[0] = GetErmResrcMonPortCtl(V, resrcMonPortEn_f, &erm_mon_port_ctl);
                value[1] = GetErmResrcMonPortCtl(V, resrcMonPortId_f, &erm_mon_port_ctl);
                value[2] = GetErmResrcMonScanCtl(V, resrcMonScanPushPortDetailedEn_f, ds);
                if(field_val == 1 && value[0] == 1 && value[1] != channel_id && value[2] == 0)
                {
                    return CTC_E_PARAM_CONFLICT;
                }
                if((field_val == 0 && value[1] == channel_id)||(field_val == 1))
                {
                    SetErmResrcMonScanCtl(V, resrcMonScanPushPortDetailedEn_f, ds, field_val);
                    cmd = DRV_IOW(ErmResrcMonPortCtl_t, ErmResrcMonPortCtl_resrcMonPortEn_f);
                    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
                    cmd = DRV_IOW(ErmResrcMonPortCtl_t, ErmResrcMonPortCtl_resrcMonPortId_f);
                    field_val = (uint32)channel_id;
                    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
                }
            }
        }
        else
        {
            return CTC_E_NOT_SUPPORT;
        }
        break;
    default:
        return CTC_E_INVALID_PARAM;
    }
    cmd = p_cfg->dir ? DRV_IOW(ErmResrcMonScanCtl_t, DRV_ENTRY_FLAG):DRV_IOW(IrmResrcMonScanCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, tbl_idx, cmd, ds));

    return CTC_E_NONE; 
}

int32
sys_usw_monitor_get_buffer_scan(uint8 lchip, uint8 tbl_idx, uint32 channel_id, ctc_monitor_config_t *p_cfg)
{
    uint32 cmd = 0;
    uint32 field_val = 0;
    uint32 value_tmp = 0;
    uint32 fvalue[SYS_CHAN_BITMAP_IN_WORD];
    ds_t ds;
    
    if (MCHIP_MON(lchip)->buffer_scan)
    {
        return MCHIP_MON(lchip)->buffer_scan(lchip, 0, p_cfg);
    }
    
    if (DRV_IS_TMG(lchip) && (CTC_MONITOR_BUFFER_PORT_SC == p_cfg->buffer_type) && (CTC_INGRESS == p_cfg->dir))
    {
        return CTC_E_NOT_SUPPORT;
    }
    cmd = p_cfg->dir ? DRV_IOR(ErmResrcMonScanCtl_t, DRV_ENTRY_FLAG): DRV_IOR(IrmResrcMonScanCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, tbl_idx, cmd, ds));
    switch(p_cfg->buffer_type)
    {
    case CTC_MONITOR_BUFFER_PORT:
        if(p_cfg->dir == CTC_EGRESS)
        {
            GetErmResrcMonScanCtl(A,  resrcMonScanPushChannelEn_f, ds, fvalue);
        }
        else
        {
            GetIrmResrcMonScanCtl(A,  resrcMonScanPushChannelEn_f, ds, fvalue);
        }
        field_val = CTC_BMP_ISSET(fvalue, tbl_idx ? (channel_id % MCHIP_CAP(SYS_CAP_PER_DP_CHANNEL_NUM)) : channel_id) ? 1 : 0;
        break;
    case CTC_MONITOR_BUFFER_PORT_SC:
        if(p_cfg->dir == CTC_EGRESS)
        {
            GetErmResrcMonScanCtl(A,  resrcMonScanPushChannelScEn_f, ds, fvalue);
        }
        else
        {
            GetIrmResrcMonScanCtl(A,  resrcMonScanPushChannelScEn_f, ds, fvalue);
        }
        field_val = CTC_BMP_ISSET(fvalue, tbl_idx ? (channel_id % MCHIP_CAP(SYS_CAP_PER_DP_CHANNEL_NUM)) : channel_id) ? 1 : 0;
        break;
    case CTC_MONITOR_BUFFER_SC:
        field_val = p_cfg->dir ? GetErmResrcMonScanCtl(V, resrcMonScanPushScEn_f, ds):GetIrmResrcMonScanCtl(V, resrcMonScanPushScEn_f, ds);
        break;
    case CTC_MONITOR_BUFFER_TOTAL:
        field_val = p_cfg->dir ? GetErmResrcMonScanCtl(V, resrcMonScanPushMiscEn_f, ds):GetIrmResrcMonScanCtl(V, resrcMonScanPushMiscEn_f, ds);
        break;
    case CTC_MONITOR_BUFFER_QUEUE:
        if(p_cfg->dir == CTC_EGRESS)
        {
            if (DRV_FROM_TMM(lchip))
            {
                cmd = DRV_IOR(ErmResrcMonScanCtl_t, ErmResrcMonScanCtl_resrcMonScanPushQueueShadowEn_f);
                CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
    
            }
            else
            {
                cmd = DRV_IOR(ErmResrcMonPortCtl_t, ErmResrcMonPortCtl_resrcMonPortEn_f);
                CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
                cmd = DRV_IOR(ErmResrcMonPortCtl_t, ErmResrcMonPortCtl_resrcMonPortId_f);
                CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value_tmp));
                field_val = (field_val && value_tmp == channel_id)? 1 : 0;
    
                value_tmp = GetErmResrcMonScanCtl(V, resrcMonScanPushPortDetailedEn_f, ds);
                field_val = field_val && value_tmp ? 1 : 0;
            }
        }
        else
        {
            return CTC_E_NOT_SUPPORT;
        }
        break;
    default:
        return CTC_E_INVALID_PARAM;
    }
    p_cfg->value = field_val;
    return CTC_E_NONE;
}

int32
sys_usw_monitor_set_latency_scan(uint8 lchip, uint32 channel_id, ctc_monitor_config_t *p_cfg)
{
    ds_t ds;
    uint32 cmd = 0;
    channel_id = channel_id&(MCHIP_CAP(SYS_CAP_MONITOR_MAX_CHANNEL) - 1);
    channel_id = SYS_USW_CHANNEL_ENCODE(channel_id); /* for TMG, chan bit7 is dpid, bit6 is not use */
    
    if (DRV_FROM_AT(lchip))
    {
        uint32 value[SYS_CHAN_BITMAP_IN_WORD];
        uint32 pp_id = 0;
        sys_usw_dmps_port_info_t dmps_port_info = {0};

        dmps_port_info.gport = p_cfg->gport;
        CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_PP_ID, &pp_id));
        pp_id += SYS_PP_BASE(lchip);
        cmd = DRV_IOR(LatencyMonScanReportCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(pp_id, 0, DRV_CMD_PP_EN(cmd), ds));
        GetLatencyMonScanReportCtl(A,  reportEn_f, ds, value);
        p_cfg->value ? CTC_BIT_SET(value[channel_id >> 5], channel_id&0x1F) : CTC_BIT_UNSET(value[channel_id >> 5], channel_id&0x1F);
        SetLatencyMonScanReportCtl(A,  reportEn_f, ds, value);
        cmd = DRV_IOW(LatencyMonScanReportCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(pp_id, 0, DRV_CMD_PP_EN(cmd), ds));
    }
    else
    {
        uint32 value[8];
        cmd = DRV_IOR(LatencyMonScanCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
        GetLatencyMonScanCtl(A,  reportEn_f, ds, value);
        p_cfg->value ? CTC_BIT_SET(value[channel_id >> 5], channel_id&0x1F) : CTC_BIT_UNSET(value[channel_id >> 5], channel_id&0x1F);
        SetLatencyMonScanCtl(A, reportEn_f, ds, value);
        cmd = DRV_IOW(LatencyMonScanCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
    }

    return CTC_E_NONE;
}

int32
sys_usw_monitor_get_latency_scan(uint8 lchip, uint32 channel_id, ctc_monitor_config_t *p_cfg)
{
    ds_t ds;
    uint32 cmd = 0;
    uint32 fvalue[SYS_CHAN_BITMAP_IN_WORD];    
    channel_id = SYS_USW_CHANNEL_ENCODE(channel_id); /* for TMG, chan bit7 is dpid, bit6 is not use */
    
    if (DRV_FROM_AT(lchip))
    {
        uint32 pp_id = 0;
        sys_usw_dmps_port_info_t dmps_port_info = {0};
        LatencyMonScanReportCtl_m lat_report_ctl;

        dmps_port_info.gport = p_cfg->gport;
        CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_PP_ID, &pp_id));
        pp_id += SYS_PP_BASE(lchip);
        cmd = DRV_IOR(LatencyMonScanReportCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(pp_id, 0, DRV_CMD_PP_EN(cmd), &lat_report_ctl));
        GetLatencyMonScanReportCtl(A,  reportEn_f, &lat_report_ctl, fvalue);
    }
    else
    {
        cmd = DRV_IOR(LatencyMonScanCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
        GetLatencyMonScanCtl(A,  reportEn_f, ds, fvalue);
    }
    p_cfg->value = CTC_IS_BIT_SET(fvalue[channel_id >> 5], channel_id&0x1F);

    return CTC_E_NONE;
}

int32
_sys_usw_monitor_set_config(uint8 lchip, ctc_monitor_config_t *p_cfg)
{
    uint32 cmd = 0;
    uint16 lport = 0;
    uint32 channel_id = 0;
    uint8 tbl_idx = 0;
    uint32 field_val = 0;
    uint32 value_tmp = 0;
    sys_usw_dmps_port_info_t dmps_port_info = {0};
    ErmResrcMonScanCtl_m ermresrc_mon_scan_ctl;
    IrmResrcMonScanCtl_m irmresrc_mon_scan_ctl;
    LatencyMonScanCtl_m latency_ctl;
#if 0
    uint32 monitorirm_en[SYS_CHAN_BITMAP_IN_WORD_DP] = {0};
    uint32 latency_en[SYS_CHAN_BITMAP_IN_WORD] = {0};
    uint32 monitorerm_en[SYS_CHAN_BITMAP_IN_WORD] = {0};
    uint32 zero_array[SYS_CHAN_BITMAP_IN_WORD] = {0};
#endif
    sys_monitor_path_config_t path_cfg;

    SYS_MONITOR_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);
    //SYS_MONITOR_INIT_CHECK();
    CTC_PTR_VALID_CHECK(p_cfg);
    CTC_MAX_VALUE_CHECK(p_cfg->sc,p_cfg->buffer_type == CTC_MONITOR_BUFFER_PORT_PRIO_CLASS? SYS_MONITOR_PRIO_CLASS_NUM - 1 : SYS_MONITOR_SC_NUM_MAX - 1);/*sc reused as priority class*/
    CTC_MAX_VALUE_CHECK(p_cfg->dir, CTC_EGRESS);

    sal_memset(&ermresrc_mon_scan_ctl, 0, sizeof(ermresrc_mon_scan_ctl));
    sal_memset(&irmresrc_mon_scan_ctl, 0, sizeof(irmresrc_mon_scan_ctl));
    sal_memset(&latency_ctl, 0, sizeof(latency_ctl));
    sal_memset(&path_cfg, 0, sizeof(sys_monitor_path_config_t));
    field_val = p_cfg->value?1:0;
    if((p_cfg->monitor_type == CTC_MONITOR_BUFFER && (p_cfg->buffer_type == CTC_MONITOR_BUFFER_PORT ||p_cfg->buffer_type == CTC_MONITOR_BUFFER_PORT_SC ||p_cfg->buffer_type == CTC_MONITOR_BUFFER_PORT_PRIO_CLASS || p_cfg->buffer_type == CTC_MONITOR_BUFFER_QUEUE)
        && (CTC_MONITOR_CONFIG_MON_SCAN_EN == p_cfg->cfg_type || CTC_MONITOR_CONFIG_MON_INFORM_MIN == p_cfg->cfg_type || CTC_MONITOR_CONFIG_MON_INFORM_MAX == p_cfg->cfg_type || CTC_MONITOR_RETRIEVE_MBURST_STATS == p_cfg->cfg_type))
        || (p_cfg->monitor_type == CTC_MONITOR_LATENCY && CTC_MONITOR_CONFIG_MON_INFORM_MIN != p_cfg->cfg_type &&  CTC_MONITOR_CONFIG_MON_INFORM_MAX != p_cfg->cfg_type &&
            CTC_MONITOR_CONFIG_MON_INTERVAL != p_cfg->cfg_type))
    {
        SYS_MAP_CTC_GPORT_TO_DRV_LPORT_WITH_CHECK(p_cfg->gport, lchip, lport);
        dmps_port_info.gport = p_cfg->gport;
        CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_CHAN_ID, &channel_id));
        /*TMM:spec see all channel, BEFORE TMM: spec see only network channel*/
        if (channel_id >= MCHIP_CAP(SYS_CAP_MONITOR_MAX_CHANNEL))
        {
            return CTC_E_INVALID_PARAM;
        }

        if(DRV_FROM_TMM(lchip) && (p_cfg->dir == 0) && channel_id >= MCHIP_CAP(SYS_CAP_MONITOR_MAX_CHANNEL) / 2)
        {
            tbl_idx = 1; /*for dp1*/
        }

    }
    switch(p_cfg->cfg_type)
    {
    case CTC_MONITOR_CONFIG_MON_INFORM_EN:
        if (p_cfg->monitor_type == CTC_MONITOR_BUFFER)
        {
            if(p_cfg->buffer_type != CTC_MONITOR_BUFFER_PORT && (DRV_IS_DUET2(lchip)))
            {
                return CTC_E_NOT_SUPPORT;
            }
            return sys_usw_monitor_set_buffer_inform(lchip, p_cfg);
        }
        else
        {
            cmd = DRV_IOW(DsDestChannel_t, DsDestChannel_latencyInformEn_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, channel_id, cmd, &field_val));
        }
        break;

    case CTC_MONITOR_CONFIG_MON_INFORM_MIN:
        field_val = p_cfg->value;
        if(p_cfg->buffer_type != CTC_MONITOR_BUFFER_PORT && (DRV_IS_DUET2(lchip)) &&
            p_cfg->monitor_type == CTC_MONITOR_BUFFER)
        {
            return CTC_E_NOT_SUPPORT;
        }
        if (p_cfg->monitor_type == CTC_MONITOR_BUFFER)
        {
            CTC_MAX_VALUE_CHECK(field_val, MCHIP_CAP(SYS_CAP_MONITOR_BUFFER_MAX_THRD));
            if(p_cfg->buffer_type == CTC_MONITOR_BUFFER_SC)
            {
                CTC_ERROR_RETURN(_sys_usw_monitor_set_thrd(lchip, CTC_MONITOR_BUFFER, p_cfg->buffer_type, 0, field_val, p_cfg->sc));
            }
            else if (p_cfg->buffer_type == CTC_MONITOR_BUFFER_PORT_PRIO_CLASS)
            {
                CTC_MAX_VALUE_CHECK(p_cfg->level, 1);
                CTC_ERROR_RETURN(_sys_usw_monitor_set_thrd(lchip, CTC_MONITOR_BUFFER, p_cfg->buffer_type, 0 + SYS_MONITOR_PRIO_CLASS_LEVEL_NUM * p_cfg->level, field_val, channel_id));
            }
            else
            {
                CTC_ERROR_RETURN(_sys_usw_monitor_set_thrd(lchip, CTC_MONITOR_BUFFER, p_cfg->buffer_type, 0, field_val, channel_id));
            }
        }
        else
        {
            /*for 32ns granularity*/
            field_val = field_val >> 5;
            cmd = DRV_IOW(EpePktProcCtl_t, EpePktProcCtl_latencyInformMinThrd_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        }
        break;
    case CTC_MONITOR_CONFIG_MON_INFORM_MAX:
        field_val = p_cfg->value;
        if(p_cfg->buffer_type != CTC_MONITOR_BUFFER_PORT && (DRV_IS_DUET2(lchip)) &&
            p_cfg->monitor_type == CTC_MONITOR_BUFFER)
        {
            return CTC_E_NOT_SUPPORT;
        }
        if (p_cfg->monitor_type == CTC_MONITOR_BUFFER)
        {
            CTC_MAX_VALUE_CHECK(field_val, MCHIP_CAP(SYS_CAP_MONITOR_BUFFER_MAX_THRD));
            if(p_cfg->buffer_type == CTC_MONITOR_BUFFER_SC)
            {
                CTC_ERROR_RETURN(_sys_usw_monitor_set_thrd(lchip, CTC_MONITOR_BUFFER, p_cfg->buffer_type, 1, field_val, p_cfg->sc));
            }
            else if (p_cfg->buffer_type == CTC_MONITOR_BUFFER_PORT_PRIO_CLASS)
            {
                CTC_MAX_VALUE_CHECK(p_cfg->level, 1);
                CTC_ERROR_RETURN(_sys_usw_monitor_set_thrd(lchip, CTC_MONITOR_BUFFER, p_cfg->buffer_type, 1 + SYS_MONITOR_PRIO_CLASS_LEVEL_NUM * p_cfg->level, field_val, channel_id));
            }
            else
            {
                CTC_ERROR_RETURN(_sys_usw_monitor_set_thrd(lchip, CTC_MONITOR_BUFFER, p_cfg->buffer_type, 1, field_val, channel_id));
            }
        }
        else
        {
            /*for 32ns granularity*/
            field_val = field_val >> 5;
            cmd = DRV_IOW(EpePktProcCtl_t, EpePktProcCtl_latencyInformMaxThrd_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        }
        break;
    case CTC_MONITOR_CONFIG_LOG_EN:
        if (p_cfg->monitor_type == CTC_MONITOR_BUFFER)
        {
            cmd = DRV_IOW(EpeMiscLogCtl_t, EpeMiscLogCtl_microburstLogEn_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        }
        else
        {
            field_val = field_val == 0 ? 0 : 0xff;
            cmd = DRV_IOW(DsDestChannel_t, DsDestChannel_latencyLogEn_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, channel_id, cmd, &field_val));
        }
        break;

    case CTC_MONITOR_CONFIG_LOG_THRD_LEVEL:
        if (p_cfg->monitor_type == CTC_MONITOR_LATENCY)
        {
            CTC_MAX_VALUE_CHECK(p_cfg->level, MCHIP_CAP(SYS_CAP_MONITOR_LATENCY_MAX_LEVEL));
            cmd = DRV_IOR(DsDestChannel_t, DsDestChannel_latencyLogEn_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, channel_id, cmd, &field_val));
            p_cfg->value ? CTC_BIT_SET(field_val, p_cfg->level) : CTC_BIT_UNSET(field_val, p_cfg->level);
            cmd = DRV_IOW(DsDestChannel_t, DsDestChannel_latencyLogEn_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, channel_id, cmd, &field_val));
        }
        else
        {
            return CTC_E_NOT_SUPPORT;
        }

        break;

    case CTC_MONITOR_CONFIG_MON_SCAN_EN:
        if (p_cfg->monitor_type == CTC_MONITOR_BUFFER)
        {
            return sys_usw_monitor_set_buffer_scan(lchip, tbl_idx, channel_id, p_cfg);
        }
        else
        {
            return sys_usw_monitor_set_latency_scan(lchip, channel_id, p_cfg);
        }
        break;

    case  CTC_MONITOR_CONFIG_MON_INTERVAL:
        CTC_ERROR_RETURN(sys_usw_monitor_set_timer(lchip, p_cfg->monitor_type, p_cfg->value));
        break;

    case  CTC_MONITOR_CONFIG_LANTENCY_DISCARD_EN:
        if(p_cfg->monitor_type == CTC_MONITOR_LATENCY)
        {
            field_val = field_val == 0 ? 0 : 0xff;
            cmd = DRV_IOW(DsDestChannel_t, DsDestChannel_latencyDiscardEn_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, channel_id, cmd, &field_val));
        }
        else
        {
            return CTC_E_NOT_SUPPORT;
        }
        break;
    case  CTC_MONITOR_CONFIG_LANTENCY_DISCARD_THRD_LEVEL:
        if(p_cfg->monitor_type == CTC_MONITOR_LATENCY)
        {
            CTC_MAX_VALUE_CHECK(p_cfg->level, MCHIP_CAP(SYS_CAP_MONITOR_LATENCY_MAX_LEVEL));
            cmd = DRV_IOR(DsDestChannel_t, DsDestChannel_latencyDiscardEn_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, channel_id, cmd, &field_val));
            p_cfg->value ? CTC_BIT_SET(field_val, p_cfg->level) : CTC_BIT_UNSET(field_val, p_cfg->level);
            cmd = DRV_IOW(DsDestChannel_t, DsDestChannel_latencyDiscardEn_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, channel_id, cmd, &field_val));
        }
        else
        {
            return CTC_E_NOT_SUPPORT;
        }
        break;
    case CTC_MONITOR_CONFIG_PATH_LANTENCY_EN:
        if (p_cfg->monitor_type == CTC_MONITOR_LATENCY && DRV_FROM_TMM(lchip))
        {
            int32 ret = CTC_E_NONE;
            cmd = DRV_IOR(EpePktProcPathMonCtl_t, EpePktProcPathMonCtl_legacyFeatureEn_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
            if (field_val == 1)
            {
                return CTC_E_NOT_SUPPORT;
            }

            SYS_MAP_CTC_GPORT_TO_DRV_LPORT_WITH_CHECK(p_cfg->src_gport, lchip, path_cfg.src_lport);
            SYS_MAP_CTC_GPORT_TO_DRV_LPORT_WITH_CHECK(p_cfg->gport, lchip, path_cfg.dst_lport);
            if (MCHIP_MON(lchip)->set_path_latency)
            {
                ret = MCHIP_MON(lchip)->set_path_latency(lchip, &path_cfg, p_cfg->value);
            }
            return ret;
        }
        else
        {
            return CTC_E_NOT_SUPPORT;
        }
    case  CTC_MONITOR_RETRIEVE_LATENCY_STATS:
        if(p_cfg->monitor_type == CTC_MONITOR_LATENCY)
        {
            CTC_MAX_VALUE_CHECK(p_cfg->level, MCHIP_CAP(SYS_CAP_MONITOR_LATENCY_MAX_LEVEL));
            for (value_tmp = 0; value_tmp < 8; value_tmp++)
            {
                p_usw_monitor_master[lchip]->latency_stats[channel_id][value_tmp] = 0;
            }
        }
        break;
    case CTC_MONITOR_RETRIEVE_MBURST_STATS:
        if(p_cfg->monitor_type == CTC_MONITOR_BUFFER)
        {
            CTC_MAX_VALUE_CHECK(p_cfg->level, MCHIP_CAP(SYS_CAP_MONITOR_LATENCY_MAX_LEVEL));
            cmd = DRV_FROM_AT(lchip) ? DRV_IOR(ErmMiscCtlUc_t, ErmMiscCtlUc_microBurstInformEn_f) : DRV_IOR(ErmMiscCtl_t, ErmMiscCtl_microBurstInformEn_f); 
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
            if(field_val == 0)
            {
                return CTC_E_INVALID_PARAM;
            }
            for (value_tmp = 0; value_tmp < 8; value_tmp++)
            {
                p_usw_monitor_master[lchip]->mburst_stats[channel_id][value_tmp] = 0;
            }
        }
        break;
    case  CTC_MONITOR_CONFIG_LANTENCY_ECN_EN:
        if(p_cfg->monitor_type == CTC_MONITOR_LATENCY)
        {
            if (DRV_FROM_AT(lchip))
            {
                field_val = field_val ? 1 : 0;
                cmd = DRV_IOW(DsDestChannel_t, DsDestChannel_latencyMarkEcn_f);
                CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, channel_id, cmd, &field_val));
                cmd = DRV_IOW(DsDestChannel_t, DsDestChannel_latencyCongestionEn_f);
            }
            else
            {
                field_val = field_val ? 0xff : 0;
                cmd = DRV_IOW(DsDestChannel_t, DsDestChannel_latencyCongestionValid_f);
            }
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, channel_id, cmd, &field_val));
        }
        else
        {
            return CTC_E_NOT_SUPPORT;
        }
        break;

    case  CTC_MONITOR_CONFIG_LANTENCY_ECN_THRD_LEVEL:
	    if (DRV_FROM_AT(lchip))
        {
            return CTC_E_NOT_SUPPORT;
        }
        if(p_cfg->monitor_type == CTC_MONITOR_LATENCY)
        {
            CTC_MAX_VALUE_CHECK(p_cfg->level, MCHIP_CAP(SYS_CAP_MONITOR_LATENCY_MAX_LEVEL));
            cmd = DRV_IOR(DsDestChannel_t, DsDestChannel_latencyCongestionValid_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, channel_id, cmd, &field_val));
            if(p_cfg->value)
            {
                CTC_BIT_SET(field_val, p_cfg->level);
            }
            else
            {
                CTC_BIT_UNSET(field_val, p_cfg->level);
            }
            cmd = DRV_IOW(DsDestChannel_t, DsDestChannel_latencyCongestionValid_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, channel_id, cmd, &field_val));
        }
        else
        {
            return CTC_E_NOT_SUPPORT;
        }
        break;
    default:
        return CTC_E_INVALID_PARAM;
    }

    return CTC_E_NONE;
}

int32
_sys_usw_monitor_get_config(uint8 lchip, ctc_monitor_config_t *p_cfg)
{
    uint32 cmd = 0;
    uint16 lport = 0;
    uint32 channel_id = 0;
    uint8  tbl_idx = 0;
    uint8  value = 0;
    uint32 field_val = 0;
    sys_usw_dmps_port_info_t dmps_port_info = {0};
    sys_monitor_path_config_t path_cfg;

    SYS_MONITOR_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);
    //SYS_MONITOR_INIT_CHECK();
    CTC_PTR_VALID_CHECK(p_cfg);
    CTC_MAX_VALUE_CHECK(p_cfg->sc,p_cfg->buffer_type == CTC_MONITOR_BUFFER_PORT_PRIO_CLASS? SYS_MONITOR_PRIO_CLASS_NUM - 1 : SYS_MONITOR_SC_NUM_MAX - 1);/*sc reused as priority class*/

    sal_memset(&path_cfg, 0, sizeof(sys_monitor_path_config_t));

    if((p_cfg->monitor_type == CTC_MONITOR_BUFFER && (p_cfg->buffer_type == CTC_MONITOR_BUFFER_PORT ||p_cfg->buffer_type == CTC_MONITOR_BUFFER_PORT_SC ||p_cfg->buffer_type == CTC_MONITOR_BUFFER_PORT_PRIO_CLASS || p_cfg->buffer_type == CTC_MONITOR_BUFFER_QUEUE)
        && (CTC_MONITOR_CONFIG_MON_SCAN_EN == p_cfg->cfg_type || CTC_MONITOR_CONFIG_MON_INFORM_MIN == p_cfg->cfg_type || CTC_MONITOR_CONFIG_MON_INFORM_MAX == p_cfg->cfg_type || CTC_MONITOR_RETRIEVE_MBURST_STATS == p_cfg->cfg_type))
        || (p_cfg->monitor_type == CTC_MONITOR_LATENCY && CTC_MONITOR_CONFIG_MON_INFORM_MIN != p_cfg->cfg_type &&  CTC_MONITOR_CONFIG_MON_INFORM_MAX != p_cfg->cfg_type &&
            CTC_MONITOR_CONFIG_MON_INTERVAL != p_cfg->cfg_type))
    {
        SYS_MAP_CTC_GPORT_TO_DRV_LPORT_WITH_CHECK(p_cfg->gport, lchip, lport);
        dmps_port_info.gport = p_cfg->gport;
        CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_CHAN_ID, &channel_id));
        if (channel_id >= MCHIP_CAP(SYS_CAP_MONITOR_MAX_CHANNEL))
        {
            return CTC_E_INVALID_PARAM;
        }

        if(DRV_FROM_TMM(lchip) && (p_cfg->dir == 0) && channel_id >= MCHIP_CAP(SYS_CAP_MONITOR_MAX_CHANNEL) / 2)
        {
            tbl_idx = 1; /*for dp1*/
        }

    }

    switch(p_cfg->cfg_type)
    {
    case CTC_MONITOR_CONFIG_MON_INFORM_EN:
        if (p_cfg->monitor_type == CTC_MONITOR_BUFFER)
        {
            return sys_usw_monitor_get_buffer_inform(lchip, p_cfg);
        }
        else
        {
            cmd = DRV_IOR(DsDestChannel_t, DsDestChannel_latencyInformEn_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, channel_id, cmd, &field_val));
            p_cfg->value = field_val;
        }
        break;
    case CTC_MONITOR_CONFIG_MON_INFORM_MIN:
        if(p_cfg->monitor_type == CTC_MONITOR_BUFFER)
        {
            if (p_cfg->buffer_type == CTC_MONITOR_BUFFER_SC)
            {
                CTC_ERROR_RETURN(_sys_usw_monitor_get_thrd(lchip, CTC_MONITOR_BUFFER, p_cfg->buffer_type, 0, &field_val, p_cfg->sc));
            }
            else if (p_cfg->buffer_type == CTC_MONITOR_BUFFER_PORT_PRIO_CLASS)
            {
                CTC_MAX_VALUE_CHECK(p_cfg->level, 1);
                CTC_ERROR_RETURN(_sys_usw_monitor_get_thrd(lchip, CTC_MONITOR_BUFFER, p_cfg->buffer_type, 0 + SYS_MONITOR_PRIO_CLASS_LEVEL_NUM * p_cfg->level, &field_val, channel_id));
            }
            else
            {
                CTC_ERROR_RETURN(_sys_usw_monitor_get_thrd(lchip, CTC_MONITOR_BUFFER, p_cfg->buffer_type, 0, &field_val, channel_id));
            }
        }
        else
        {
            cmd = DRV_IOR(EpePktProcCtl_t, EpePktProcCtl_latencyInformMinThrd_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
            field_val = (field_val << 5);
        }
        p_cfg->value = field_val;
        break;

    case CTC_MONITOR_CONFIG_MON_INFORM_MAX:
        if(p_cfg->monitor_type == CTC_MONITOR_BUFFER)
        {
            if ( p_cfg->buffer_type == CTC_MONITOR_BUFFER_SC)
            {
                CTC_ERROR_RETURN(_sys_usw_monitor_get_thrd(lchip, CTC_MONITOR_BUFFER, p_cfg->buffer_type, 1, &field_val, p_cfg->sc));
            }
            else if (p_cfg->buffer_type == CTC_MONITOR_BUFFER_PORT_PRIO_CLASS)
            {
                CTC_MAX_VALUE_CHECK(p_cfg->level, 1);
                CTC_ERROR_RETURN(_sys_usw_monitor_get_thrd(lchip, CTC_MONITOR_BUFFER, p_cfg->buffer_type, 1 + SYS_MONITOR_PRIO_CLASS_LEVEL_NUM * p_cfg->level, &field_val, channel_id));
            }
            else
            {
                CTC_ERROR_RETURN(_sys_usw_monitor_get_thrd(lchip, CTC_MONITOR_BUFFER, p_cfg->buffer_type, 1, &field_val, channel_id));
            }
        }
        else
        {
            cmd = DRV_IOR(EpePktProcCtl_t, EpePktProcCtl_latencyInformMaxThrd_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
            field_val = (field_val << 5);
        }
        p_cfg->value = field_val;
        break;


    case CTC_MONITOR_CONFIG_LOG_EN:

        if (p_cfg->monitor_type == CTC_MONITOR_BUFFER)
        {
            cmd = DRV_IOR(EpeMiscLogCtl_t, EpeMiscLogCtl_microburstLogEn_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        }
        else
        {
            cmd = DRV_IOR(DsDestChannel_t, DsDestChannel_latencyLogEn_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, channel_id, cmd, &field_val));
            field_val = field_val?1:0;
        }
        p_cfg->value = field_val;
        break;

    case CTC_MONITOR_CONFIG_LOG_THRD_LEVEL:
        if (p_cfg->monitor_type == CTC_MONITOR_LATENCY)
        {
            cmd = DRV_IOR(DsDestChannel_t, DsDestChannel_latencyLogEn_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, channel_id, cmd, &field_val));
        }
        p_cfg->level = field_val;
        break;

    case CTC_MONITOR_CONFIG_MON_SCAN_EN:
        if (p_cfg->monitor_type == CTC_MONITOR_BUFFER)
        {
            return sys_usw_monitor_get_buffer_scan(lchip, tbl_idx, channel_id, p_cfg);
        }
        else
        {
            return sys_usw_monitor_get_latency_scan(lchip, channel_id, p_cfg);
        }
        break;

    case  CTC_MONITOR_CONFIG_MON_INTERVAL:
        CTC_ERROR_RETURN(sys_usw_monitor_get_timer(lchip, p_cfg->monitor_type, &p_cfg->value));
        break;

    case  CTC_MONITOR_CONFIG_LANTENCY_DISCARD_EN:
        if(p_cfg->monitor_type == CTC_MONITOR_LATENCY)
        {
            cmd = DRV_IOR(DsDestChannel_t, DsDestChannel_latencyDiscardEn_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, channel_id, cmd, &field_val));
            field_val = field_val?1:0;
        }
        p_cfg->value = field_val;
        break;

    case  CTC_MONITOR_CONFIG_LANTENCY_DISCARD_THRD_LEVEL:
        if(p_cfg->monitor_type == CTC_MONITOR_LATENCY)
        {
            cmd = DRV_IOR(DsDestChannel_t, DsDestChannel_latencyDiscardEn_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, channel_id, cmd, &field_val));
        }
        p_cfg->level = field_val;
        break;
    case CTC_MONITOR_CONFIG_PATH_LANTENCY_EN:
        if (p_cfg->monitor_type == CTC_MONITOR_LATENCY && DRV_FROM_TMM(lchip))
        {
            SYS_MAP_CTC_GPORT_TO_DRV_LPORT_WITH_CHECK(p_cfg->src_gport, lchip, path_cfg.src_lport);
            SYS_MAP_CTC_GPORT_TO_DRV_LPORT_WITH_CHECK(p_cfg->gport, lchip, path_cfg.dst_lport);
            if(MCHIP_MON(lchip)->get_path_latency)
            {
                CTC_ERROR_RETURN(MCHIP_MON(lchip)->get_path_latency(lchip, &path_cfg, &value));
            }
        }
        p_cfg->value = value;
        break;
    case  CTC_MONITOR_RETRIEVE_LATENCY_STATS:
        if(p_cfg->monitor_type == CTC_MONITOR_LATENCY)
        {
            CTC_MAX_VALUE_CHECK(p_cfg->level, MCHIP_CAP(SYS_CAP_MONITOR_LATENCY_MAX_LEVEL));
            p_cfg->value = p_usw_monitor_master[lchip]->latency_stats[channel_id][p_cfg->level];
            p_cfg->value1 = p_usw_monitor_master[lchip]->latency_stats[channel_id][p_cfg->level] >> CTC_UINT32_BITS;
        }
        break;
    case CTC_MONITOR_RETRIEVE_MBURST_STATS:
        if(p_cfg->monitor_type == CTC_MONITOR_BUFFER)
        {
            CTC_MAX_VALUE_CHECK(p_cfg->level, MCHIP_CAP(SYS_CAP_MONITOR_LATENCY_MAX_LEVEL));
            if (DRV_FROM_AT(lchip))
            {
                cmd = DRV_IOR(ErmMiscCtlUc_t, ErmMiscCtlUc_microBurstInformEn_f);
            }
            else
            {
                cmd = DRV_IOR(ErmMiscCtl_t, ErmMiscCtl_microBurstInformEn_f);
            }
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
            if(field_val == 0)
            {
                return CTC_E_INVALID_PARAM;
            }
            p_cfg->value = p_usw_monitor_master[lchip]->mburst_stats[channel_id][p_cfg->level];
            p_cfg->value1 = p_usw_monitor_master[lchip]->mburst_stats[channel_id][p_cfg->level] >> CTC_UINT32_BITS;
        }
        break;
    case  CTC_MONITOR_CONFIG_LANTENCY_ECN_EN:
        if(p_cfg->monitor_type == CTC_MONITOR_LATENCY)
        {
            cmd = DRV_IOR(DsDestChannel_t, DRV_FROM_AT(lchip) ? DsDestChannel_latencyMarkEcn_f : DsDestChannel_latencyCongestionValid_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, channel_id, cmd, &field_val));
            field_val = field_val?1:0;
        }
        p_cfg->value = field_val;
        break;

    case  CTC_MONITOR_CONFIG_LANTENCY_ECN_THRD_LEVEL:
        if (DRV_FROM_AT(lchip))
        {
            return CTC_E_NOT_SUPPORT;
        }
        if(p_cfg->monitor_type == CTC_MONITOR_LATENCY)
        {
            cmd = DRV_IOR(DsDestChannel_t, DsDestChannel_latencyCongestionValid_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, channel_id, cmd, &field_val));
        }
        p_cfg->level = field_val;
        break;
    default:
        return CTC_E_INVALID_PARAM;
    }

    return CTC_E_NONE;

}

#define SYS_USW_MONITOR_MAX_BUFFER_THRD 0x3FFFF
int32
sys_usw_monitor_set_snapshot_thrd(uint8 lchip, void* p_cfg)
{
    uint32 cmd = 0;
    uint32 tbl_id = 0;
    uint32 threshold = 0;
    uint8 step = 0;
    ds_t  ds;
    ctc_monitor_buffer_snapshot_t* p_snapshot = (ctc_monitor_buffer_snapshot_t* )p_cfg;
    threshold = (p_snapshot->threshold > SYS_USW_MONITOR_MAX_BUFFER_THRD) ? SYS_USW_MONITOR_MAX_BUFFER_THRD : p_snapshot->threshold;

    tbl_id = p_snapshot->dir ? ErmResrcMonCtl_t : IrmResrcMonCtl_t;
    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));    
    switch (p_snapshot->buffer_type)
    {
        case CTC_MONITOR_BUFFER_SC:
            step = IrmResrcMonCtl_trigger_scCnt1_f - IrmResrcMonCtl_trigger_scCnt0_f;
            CTC_MAX_VALUE_CHECK(p_snapshot->sc, SYS_MONITOR_SC_NUM_MAX - 1);
            SetErmResrcMonCtl(V, trigger_scCnt0_f + step * p_snapshot->sc, &ds, threshold);
            break;
        case CTC_MONITOR_BUFFER_C2C:
            SetErmResrcMonCtl(V, trigger_c2cCnt_f, &ds, threshold);
            break;
        case CTC_MONITOR_BUFFER_CONTROL:
            SetErmResrcMonCtl(V, trigger_criticalCnt_f, &ds, threshold);
            break;
        case CTC_MONITOR_BUFFER_TOTAL:
            SetErmResrcMonCtl(V, trigger_totalCnt_f, &ds, threshold);
            break;
        case CTC_MONITOR_BUFFER_ROUND_TRIP:
            CTC_MAX_VALUE_CHECK(p_snapshot->dir, CTC_INGRESS);
            cmd = DRV_IOR(IrmResrcMonHeadroomCtl_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
            SetIrmResrcMonHeadroomCtl(V, trigger_headroomCnt_f, &ds, threshold);
            tbl_id = IrmResrcMonHeadroomCtl_t;
            break;
        default:
            return CTC_E_NOT_SUPPORT;
    }
    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));

    tbl_id = p_snapshot->dir ? ErmResrcMonState_t : IrmResrcMonState_t;
    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
    SetErmResrcMonState(V, resrcShadowLock_f, &ds, 0);
    cmd = DRV_IOW(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));

    return CTC_E_NONE;
}

int32
sys_usw_monitor_get_snapshot_thrd(uint8 lchip, void* p_cfg)
{
    uint32 cmd = 0;
    uint32 tbl_id = 0;
    uint8 step = 0;
    ds_t  ds;
    ctc_monitor_buffer_snapshot_t* p_snapshot = (ctc_monitor_buffer_snapshot_t* )p_cfg;

    tbl_id = p_snapshot->dir ? ErmResrcMonCtl_t : IrmResrcMonCtl_t;
    cmd = DRV_IOR(tbl_id, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
    switch (p_snapshot->buffer_type)
    {
        case CTC_MONITOR_BUFFER_SC:
            step = IrmResrcMonCtl_trigger_scCnt1_f - IrmResrcMonCtl_trigger_scCnt0_f;
            CTC_MAX_VALUE_CHECK(p_snapshot->sc, SYS_MONITOR_SC_NUM_MAX - 1);
            p_snapshot->threshold = GetErmResrcMonCtl(V, trigger_scCnt0_f + step * p_snapshot->sc, &ds);
            break;
        case CTC_MONITOR_BUFFER_C2C:
            p_snapshot->threshold = GetErmResrcMonCtl(V, trigger_c2cCnt_f, &ds);
            break;
        case CTC_MONITOR_BUFFER_CONTROL:
            p_snapshot->threshold = GetErmResrcMonCtl(V, trigger_criticalCnt_f, &ds);
            break;
        case CTC_MONITOR_BUFFER_TOTAL:
            p_snapshot->threshold = GetErmResrcMonCtl(V, trigger_totalCnt_f, &ds);
            break;
        case CTC_MONITOR_BUFFER_ROUND_TRIP:
            CTC_MAX_VALUE_CHECK(p_snapshot->dir, CTC_INGRESS);
            cmd = DRV_IOR(IrmResrcMonHeadroomCtl_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
            p_snapshot->threshold = GetIrmResrcMonHeadroomCtl(V, trigger_headroomCnt_f, &ds);    
            break;
        default:
            return CTC_E_NOT_SUPPORT;
    }

    return CTC_E_NONE;
}

/*from AT, new config type support*/
int32
_sys_usw_monitor_set_config2(uint8 lchip, ctc_monitor_config_type_t type, void* p_cfg)
{
    uint32 cmd = 0;

    ds_t ds;
    SYS_MONITOR_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);
    //SYS_MONITOR_INIT_CHECK();
    CTC_PTR_VALID_CHECK(p_cfg);

    sal_memset(&ds, 0, sizeof(ds_t));
    switch (type)
    {
        case CTC_MONITOR_CONFIG_BUFFER_SNAPSHOT_THRD:
        {
            CTC_ERROR_RETURN(sys_usw_monitor_set_snapshot_thrd(lchip, p_cfg));
        }
            break;
        case CTC_MONITOR_CONFIG_LATENCY_ECN_THRD:
        {
            uint32 channel_id = 0;
            uint16 lport = 0;
            sys_usw_dmps_port_info_t dmps_port_info = {0};
            ctc_monitor_latency_ecn_thrd_t* p_latency_ecn = (ctc_monitor_latency_ecn_thrd_t*)p_cfg;

            SYS_MAP_CTC_GPORT_TO_DRV_LPORT_WITH_CHECK(p_latency_ecn->gport, lchip, lport);
            CTC_MAX_VALUE_CHECK(p_latency_ecn->off_thrd >> 5, 0xFFFF);
            CTC_MAX_VALUE_CHECK(p_latency_ecn->on_thrd >> 5, 0xFFFFFF);
            CTC_MAX_VALUE_CHECK(p_latency_ecn->off_thrd, p_latency_ecn->on_thrd);
            dmps_port_info.gport = p_latency_ecn->gport;
            CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_CHAN_ID, &channel_id));
            if (SYS_DMPS_INVALID_CHAN_ID == channel_id)
            {
                return CTC_E_INVALID_PARAM;
            }
            CTC_MAX_VALUE_CHECK(p_latency_ecn->level, 1);

            cmd = DRV_IOR(DsDestChannel_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, channel_id, cmd, &ds));
            if (p_latency_ecn->level)
            {
                SetDsDestChannel(V, g_1_latencyCongestionThrdL_f, &ds, p_latency_ecn->off_thrd >> 5);
                SetDsDestChannel(V, g_1_latencyCongestionThrdH_f, &ds, p_latency_ecn->on_thrd >> 5);
            }
            else
            {
                SetDsDestChannel(V, g_0_latencyCongestionThrdL_f, &ds, p_latency_ecn->off_thrd >> 5);
                SetDsDestChannel(V, g_0_latencyCongestionThrdH_f, &ds, p_latency_ecn->on_thrd >> 5);
            }
            cmd = DRV_IOW(DsDestChannel_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, channel_id, cmd, &ds));
        }
            break;
        case CTC_MONITOR_CONFIG_LATENCY_ECN_PRIO_MAP:
        {
            uint32 value = 0;
            ctc_monitor_latency_ecn_prio_map_t *p_map = (ctc_monitor_latency_ecn_prio_map_t *)p_cfg;

            CTC_MAX_VALUE_CHECK(p_map->priority, 15);
            cmd = DRV_IOR(EpePktProcCtl_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
            if(p_map->level != CTC_MAX_UINT8_VALUE)
            {
                CTC_MAX_VALUE_CHECK(p_map->level, 1);                
                value = GetEpePktProcCtl(V, latencyPrioMap_f, &ds);
                p_map->level ? CTC_BIT_SET(value, p_map->priority) : CTC_BIT_UNSET(value, p_map->priority);
                SetEpePktProcCtl(V, latencyPrioMap_f, &ds, value);
            }
            value = GetEpePktProcCtl(V, latencyPrioMapEn_f, &ds);
            p_map->level == CTC_MAX_UINT8_VALUE ? CTC_BIT_UNSET(value, p_map->priority) : CTC_BIT_SET(value, p_map->priority);
            SetEpePktProcCtl(V, latencyPrioMapEn_f, &ds, value);
            cmd = DRV_IOW(EpePktProcCtl_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
        }
            break;
        default:
            SYS_MONITOR_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "Invalid Config Type:%u\n", type);
            return CTC_E_INVALID_PARAM;
    }

    return CTC_E_NONE;
}

/*from AT, new config type support*/
int32
_sys_usw_monitor_get_config2(uint8 lchip, ctc_monitor_config_type_t type, void* p_cfg)
{
    uint32 cmd = 0;
    ds_t ds;
    SYS_MONITOR_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);
    //SYS_MONITOR_INIT_CHECK();
    CTC_PTR_VALID_CHECK(p_cfg);

    switch (type)
    {
        case CTC_MONITOR_CONFIG_BUFFER_SNAPSHOT_THRD:
        {
            CTC_ERROR_RETURN(sys_usw_monitor_get_snapshot_thrd(lchip, p_cfg));
        }
            break;
        case CTC_MONITOR_CONFIG_LATENCY_ECN_THRD:
        {
            uint32 channel_id = 0;
            uint16 lport = 0;
            sys_usw_dmps_port_info_t dmps_port_info = {0};
            ctc_monitor_latency_ecn_thrd_t *p_latency_ecn = (ctc_monitor_latency_ecn_thrd_t *)p_cfg;

            SYS_MAP_CTC_GPORT_TO_DRV_LPORT_WITH_CHECK(p_latency_ecn->gport, lchip, lport);
            dmps_port_info.gport = p_latency_ecn->gport;
            CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_CHAN_ID, &channel_id));
            if (SYS_DMPS_INVALID_CHAN_ID == channel_id)
            {
                return CTC_E_INVALID_PARAM;
            }
            CTC_MAX_VALUE_CHECK(p_latency_ecn->level, 1);

            cmd = DRV_IOR(DsDestChannel_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, channel_id, cmd, &ds));
            p_latency_ecn->off_thrd = p_latency_ecn->level ? GetDsDestChannel(V, g_1_latencyCongestionThrdL_f, &ds)
                                                           : GetDsDestChannel(V, g_0_latencyCongestionThrdL_f, &ds);
            p_latency_ecn->on_thrd = p_latency_ecn->level ? GetDsDestChannel(V, g_1_latencyCongestionThrdH_f, &ds)
                                                          : GetDsDestChannel(V, g_0_latencyCongestionThrdH_f, &ds);
            p_latency_ecn->off_thrd <<= 5;
            p_latency_ecn->on_thrd <<= 5;

        }
            break;
        case CTC_MONITOR_CONFIG_LATENCY_ECN_PRIO_MAP:
        {
            uint32 value = 0;
            ctc_monitor_latency_ecn_prio_map_t *p_map = (ctc_monitor_latency_ecn_prio_map_t *)p_cfg;

            CTC_MAX_VALUE_CHECK(p_map->priority, 15);
            cmd = DRV_IOR(EpePktProcCtl_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
            value = GetEpePktProcCtl(V, latencyPrioMapEn_f, &ds);
            if(CTC_IS_BIT_SET(value, p_map->priority))
            {
                value = GetEpePktProcCtl(V, latencyPrioMap_f, &ds);
                p_map->level = CTC_IS_BIT_SET(value, p_map->priority);
            }
            else
            {
                p_map->level = CTC_MAX_UINT8_VALUE;
            }
        }
            break;
        default:
            SYS_MONITOR_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, "Invalid Config Type:%u\n", type);
            return CTC_E_INVALID_PARAM;
    }

    return CTC_E_NONE;
}



int32
_sys_usw_monitor_get_watermark(uint8 lchip, ctc_monitor_watermark_t *p_watermark)
{
   uint32 cmd = 0;
   uint32 step = 0;
   uint32 channel_id = 0;
   uint16 lport = 0;
   uint32 uc_cnt = 0;
   uint32 mc_cnt = 0;
   uint32 total_cnt = 0;
   uint32 field_value = 0;
   uint64 latency_value = 0;
   sys_usw_dmps_port_info_t dmps_port_info = {0};

   SYS_MONITOR_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n",__FUNCTION__);
   SYS_MONITOR_INIT_CHECK();
   if((p_watermark->u.buffer.buffer_type == CTC_MONITOR_BUFFER_PORT && p_watermark->monitor_type == CTC_MONITOR_BUFFER)
        || p_watermark->monitor_type == CTC_MONITOR_LATENCY)
   {
       SYS_MAP_CTC_GPORT_TO_DRV_LPORT_WITH_CHECK(p_watermark->gport, lchip, lport);
       dmps_port_info.index = CTC_MAP_GPORT_TO_MCHAN_IDX(p_watermark->gport);
       dmps_port_info.gport = p_watermark->gport;
       CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_CHAN_ID, &channel_id));
       if (channel_id >= MCHIP_CAP(SYS_CAP_MONITOR_MAX_CHANNEL))
       {
           return CTC_E_INVALID_PARAM;
       }
   }

   channel_id = channel_id&(MCHIP_CAP(SYS_CAP_MONITOR_MAX_CHANNEL) - 1);

   if (p_watermark->monitor_type == CTC_MONITOR_BUFFER)
   {
       if(MCHIP_MON(lchip)->op_buffer_watermark)
       {
           return MCHIP_MON(lchip)->op_buffer_watermark(lchip, p_watermark, 0);
       }
       switch (p_watermark->u.buffer.buffer_type)
       {
       case CTC_MONITOR_BUFFER_PORT :
       if(CTC_EGRESS == p_watermark->u.buffer.dir)
       {
           cmd = DRV_IOR(DsErmResrcMonPortMax_t, DsErmResrcMonPortMax_ucastCntMax_f);
           CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, channel_id, cmd, &uc_cnt));
           cmd = DRV_IOR(DsErmResrcMonPortMax_t, DsErmResrcMonPortMax_mcastCntMax_f);
           CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, channel_id, cmd, &mc_cnt));
           cmd = DRV_IOR(DsErmResrcMonPortMax_t, DsErmResrcMonPortMax_totalCntMax_f);
           CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, channel_id, cmd, &total_cnt));

           p_watermark->u.buffer.max_uc_cnt = uc_cnt;
           p_watermark->u.buffer.max_mc_cnt = mc_cnt;
           p_watermark->u.buffer.max_total_cnt = total_cnt;
       }
       else
       {
           cmd = DRV_IOR(DsIrmResrcMonPortMax_t, DsIrmResrcMonPortMax_totalCntMax_f);
           CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, channel_id, cmd, &total_cnt));
           p_watermark->u.buffer.max_total_cnt = total_cnt;
       }
       break;

       case CTC_MONITOR_BUFFER_TOTAL :
       if(CTC_EGRESS == p_watermark->u.buffer.dir)
       {
           cmd = DRV_IOR(DsErmResrcMonMiscMax_t, DsErmResrcMonMiscMax_totalCntMax_f);
           CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &total_cnt));
           p_watermark->u.buffer.max_total_cnt = total_cnt;
       }
       else
       {
           cmd = DRV_IOR(DsIrmResrcMonMiscMax_t, DsIrmResrcMonMiscMax_totalCntMax_f);
           CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &total_cnt));
           p_watermark->u.buffer.max_total_cnt = total_cnt;
       }
       break;

       case CTC_MONITOR_BUFFER_C2C :
       if(CTC_EGRESS == p_watermark->u.buffer.dir)
       {
           cmd = DRV_IOR(DsErmResrcMonMiscMax_t, DsErmResrcMonMiscMax_c2cCntMax_f);
           CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &total_cnt));
           p_watermark->u.buffer.max_total_cnt = total_cnt;
       }
       else
       {
           cmd = DRV_IOR(DsIrmResrcMonMiscMax_t, DsIrmResrcMonMiscMax_c2cCntMax_f);
           CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &total_cnt));
           p_watermark->u.buffer.max_total_cnt = total_cnt;
       }
       break;

       case CTC_MONITOR_BUFFER_CONTROL :
       if(CTC_EGRESS == p_watermark->u.buffer.dir)
       {
           cmd = DRV_IOR(DsErmResrcMonMiscMax_t, DsErmResrcMonMiscMax_criticalCntMax_f);
           CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &total_cnt));
           p_watermark->u.buffer.max_total_cnt = total_cnt;
       }
       else
       {
           cmd = DRV_IOR(DsIrmResrcMonMiscMax_t, DsIrmResrcMonMiscMax_criticalCntMax_f);
           CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &total_cnt));
           p_watermark->u.buffer.max_total_cnt = total_cnt;
       }
       break;

       case CTC_MONITOR_BUFFER_SC :
       CTC_MAX_VALUE_CHECK(p_watermark->u.buffer.sc, SYS_MONITOR_SC_NUM_MAX - 1);
       step = DsErmResrcMonMiscMax_g_1_scCntMax_f - DsErmResrcMonMiscMax_g_0_scCntMax_f;
       if(CTC_EGRESS == p_watermark->u.buffer.dir)
       {
           cmd = DRV_IOR(DsErmResrcMonMiscMax_t, DsErmResrcMonMiscMax_g_0_scCntMax_f + step*p_watermark->u.buffer.sc);
           CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &total_cnt));
           p_watermark->u.buffer.max_total_cnt = total_cnt;
       }
       else
       {
           cmd = DRV_IOR(DsIrmResrcMonMiscMax_t, DsIrmResrcMonMiscMax_g_0_scCntMax_f + step*p_watermark->u.buffer.sc);
           CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &total_cnt));
           p_watermark->u.buffer.max_total_cnt = total_cnt;
       }
       break;
       case CTC_MONITOR_BUFFER_QUEUE:
       if(CTC_EGRESS == p_watermark->u.buffer.dir)
       {
           return _sys_usw_monitor_get_queue_watermark(lchip, p_watermark);
       }
       else
       {
           return CTC_E_NOT_SUPPORT;
       }
       break;
       default:
           return CTC_E_INVALID_PARAM;
       }
   }
   else
   {
       if (DRV_FROM_TMM(lchip))
       {
            if(MCHIP_MON(lchip)->get_path_latency_watermark)
            {
                /*sdk use 8 queue per group in [0,8K]*/
                CTC_MAX_VALUE_CHECK(p_watermark->queue.queue_id,MCHIP_CAP(SYS_CAP_QOS_QUEUE_NUM_PER_CHAN) - 1);
                return MCHIP_MON(lchip)->get_path_latency_watermark(lchip, p_watermark, channel_id);
            }
       }
       else
       {
           cmd = DRV_IOR(DsLatencyWatermark_t, DsLatencyWatermark_latencyMax_f);
           CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, channel_id, cmd, &field_value));
           latency_value = field_value;
           p_watermark->u.latency.max_latency = latency_value << 5;
       }
   }
   return CTC_E_NONE;
}

int32
_sys_usw_monitor_clear_watermark(uint8 lchip, ctc_monitor_watermark_t *p_watermark)
{
   uint32 cmd = 0;
   uint16 lport = 0;
   uint32 step = 0;
   uint32 channel_id = 0;
   uint32 uc_cnt = 0;
   uint32 mc_cnt = 0;
   uint32 total_cnt = 0;
   uint32 field_value = 0;
   sys_usw_dmps_port_info_t dmps_port_info = {0};

   SYS_MONITOR_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n",__FUNCTION__);
   SYS_MONITOR_INIT_CHECK();
   if((p_watermark->u.buffer.buffer_type == CTC_MONITOR_BUFFER_PORT && p_watermark->monitor_type == CTC_MONITOR_BUFFER)
        || p_watermark->monitor_type == CTC_MONITOR_LATENCY)
   {
       SYS_MAP_CTC_GPORT_TO_DRV_LPORT_WITH_CHECK(p_watermark->gport, lchip, lport);
       dmps_port_info.index = CTC_MAP_GPORT_TO_MCHAN_IDX(p_watermark->gport);
       dmps_port_info.gport = p_watermark->gport;
       CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_CHAN_ID, &channel_id));
       if (channel_id >= MCHIP_CAP(SYS_CAP_MONITOR_MAX_CHANNEL) )
       {
           return CTC_E_INVALID_PARAM;
       }
   }

   channel_id = channel_id&(MCHIP_CAP(SYS_CAP_MONITOR_MAX_CHANNEL) - 1);

   if (p_watermark->monitor_type == CTC_MONITOR_BUFFER)
   {
       if(MCHIP_MON(lchip)->op_buffer_watermark)
       {
           return MCHIP_MON(lchip)->op_buffer_watermark(lchip, p_watermark, 1);
       }
       switch (p_watermark->u.buffer.buffer_type)
       {
       case CTC_MONITOR_BUFFER_PORT :
       if(CTC_EGRESS == p_watermark->u.buffer.dir)
       {
           cmd = DRV_IOW(DsErmResrcMonPortMax_t, DsErmResrcMonPortMax_ucastCntMax_f);
           CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, channel_id, cmd, &uc_cnt));
           cmd = DRV_IOW(DsErmResrcMonPortMax_t, DsErmResrcMonPortMax_mcastCntMax_f);
           CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, channel_id, cmd, &mc_cnt));
           cmd = DRV_IOW(DsErmResrcMonPortMax_t, DsErmResrcMonPortMax_totalCntMax_f);
           CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, channel_id, cmd, &total_cnt));
       }
       else
       {
           cmd = DRV_IOW(DsIrmResrcMonPortMax_t, DsIrmResrcMonPortMax_totalCntMax_f);
           CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, channel_id, cmd, &total_cnt));
       }
       break;

       case CTC_MONITOR_BUFFER_TOTAL :
       if(CTC_EGRESS == p_watermark->u.buffer.dir)
       {
           cmd = DRV_IOW(DsErmResrcMonMiscMax_t, DsErmResrcMonMiscMax_totalCntMax_f);
           CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &total_cnt));
       }
       else
       {
           cmd = DRV_IOW(DsIrmResrcMonMiscMax_t, DsIrmResrcMonMiscMax_totalCntMax_f);
           CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &total_cnt));
       }
       break;

       case CTC_MONITOR_BUFFER_C2C :
       if(CTC_EGRESS == p_watermark->u.buffer.dir)
       {
           cmd = DRV_IOW(DsErmResrcMonMiscMax_t, DsErmResrcMonMiscMax_c2cCntMax_f);
           CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &total_cnt));
       }
       else
       {
           cmd = DRV_IOW(DsIrmResrcMonMiscMax_t, DsIrmResrcMonMiscMax_c2cCntMax_f);
           CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &total_cnt));
       }
       break;

       case CTC_MONITOR_BUFFER_CONTROL :
       if(CTC_EGRESS == p_watermark->u.buffer.dir)
       {
           cmd = DRV_IOW(DsErmResrcMonMiscMax_t, DsErmResrcMonMiscMax_criticalCntMax_f);
           CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &total_cnt));
       }
       else
       {
           cmd = DRV_IOW(DsIrmResrcMonMiscMax_t, DsIrmResrcMonMiscMax_criticalCntMax_f);
           CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &total_cnt));
       }
       break;

       case CTC_MONITOR_BUFFER_SC :
       CTC_MAX_VALUE_CHECK(p_watermark->u.buffer.sc, SYS_MONITOR_SC_NUM_MAX - 1);
       step = DsErmResrcMonMiscMax_g_1_scCntMax_f - DsErmResrcMonMiscMax_g_0_scCntMax_f;
       if(CTC_EGRESS == p_watermark->u.buffer.dir)
       {
           cmd = DRV_IOW(DsErmResrcMonMiscMax_t, DsErmResrcMonMiscMax_g_0_scCntMax_f + step*p_watermark->u.buffer.sc);
           CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &total_cnt));
       }
       else
       {
           cmd = DRV_IOW(DsIrmResrcMonMiscMax_t, DsIrmResrcMonMiscMax_g_0_scCntMax_f + step*p_watermark->u.buffer.sc);
           CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &total_cnt));
       }
       break;
       case CTC_MONITOR_BUFFER_QUEUE:
       if(CTC_EGRESS == p_watermark->u.buffer.dir)
       {
           return _sys_usw_monitor_clear_queue_watermark(lchip, p_watermark);
       }
       else
       {
           return CTC_E_NOT_SUPPORT;
       }
       break;
       default:
           return CTC_E_INVALID_PARAM;
       }
   }
   else
   {
       if (DRV_FROM_TMM(lchip))
       {
           if(MCHIP_MON(lchip)->clear_path_latency_watermark)
           {
               /*sdk use 8 queue per group in [0,8K]*/
               CTC_MAX_VALUE_CHECK(p_watermark->queue.queue_id,MCHIP_CAP(SYS_CAP_QOS_QUEUE_NUM_PER_CHAN) - 1);
               return MCHIP_MON(lchip)->clear_path_latency_watermark(lchip, p_watermark, channel_id);
           }
       }
       else
       {
           cmd = DRV_IOW(DsLatencyWatermark_t, DsLatencyWatermark_latencyMax_f);
           CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, channel_id, cmd, &field_value));
       }
   }

    return CTC_E_NONE;
}

/*every slice alloc 48 ports*/
int32
sys_usw_monitor_sync_queue_stats(uint8 lchip, void* p_data)
{
    /*sys_dma_reg_t* p_dma_reg = (sys_dma_reg_t*)p_data;
    uint8 slice_id = 0;
    uint8* p_addr = NULL;

    slice_id = *((uint8*)p_dma_reg->p_ext);
    p_addr = p_dma_reg->p_data;*/

     /*-ctc_monitor_queue_sample_export(slice_id, p_addr);*/
    /* TODO later, using common cb */
    return CTC_E_NONE;
}



int32
sys_usw_monitor_register_cb(uint8 lchip, ctc_monitor_fn_t callback, void* userdata)
{
    SYS_MONITOR_INIT_CHECK();
    SYS_MONITOR_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);
    MONITOR_LOCK;
    p_usw_monitor_master[lchip]->func = callback;
    p_usw_monitor_master[lchip]->user_data = userdata;
    MONITOR_UNLOCK;
    return CTC_E_NONE;
}


int32
sys_usw_monitor_get_cb(uint8 lchip, void **cb, void** user_data)
{
    MONITOR_LOCK;
    *cb = p_usw_monitor_master[lchip]->func;
    *user_data = p_usw_monitor_master[lchip]->user_data;
    MONITOR_UNLOCK;
    return CTC_E_NONE;
}



int32
_sys_usw_monitor_set_global_config(uint8 lchip, ctc_monitor_glb_cfg_t* p_cfg)
{
    uint32 cmd = 0;
    uint32 value = 0;
    uint32 loop = 0;
    uint32 entry_num = 0;
    uint8  porttc_mb_en = 0;
    DsDestChannel_m dest_chan;
    PreBufferRetrieveCtl_m br_ctl;

    SYS_MONITOR_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);
    //SYS_MONITOR_INIT_CHECK();
    CTC_PTR_VALID_CHECK(p_cfg);

    switch(p_cfg->cfg_type)
    {
    case  CTC_MONITOR_GLB_CONFIG_LATENCY_THRD:
        CTC_MAX_VALUE_CHECK(p_cfg->u.thrd.level, MCHIP_CAP(SYS_CAP_MONITOR_LATENCY_MAX_LEVEL));
        value = p_cfg->u.thrd.threshold >> 5;
        /*CTC_ERROR_RETURN(_sys_usw_monitor_thrd_check(lchip, p_cfg->u.thrd.level, p_cfg->u.thrd.threshold,CTC_MONITOR_GLB_CONFIG_LATENCY_THRD));*/
        CTC_ERROR_RETURN(
            _sys_usw_monitor_set_thrd(lchip, CTC_MONITOR_LATENCY,0, p_cfg->u.thrd.level, value, 0));

        break;

    case  CTC_MONITOR_GLB_CONFIG_BUFFER_LOG_MODE:
        CTC_MAX_VALUE_CHECK(p_cfg->u.value, 2);
        sys_usw_ftm_query_table_entry_num(lchip, DsDestChannel_t, &entry_num);
        for (loop = 0; loop < entry_num; loop++)
        {
            cmd = DRV_IOR(DsDestChannel_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, loop, cmd, &dest_chan));
            value = GetDsDestChannel(V, microburstAsCongestion_f, &dest_chan);
            if(value)
            {
                return CTC_E_INVALID_PARAM;
            }
        }
        cmd = DRV_IOR(PreBufferRetrieveCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &br_ctl));    
        porttc_mb_en = GetPreBufferRetrieveCtl(V, mbTcMode_f, &br_ctl);
        if (DRV_FROM_AT(lchip))
        {
            if (SYS_MONITOR_LOG_MODE_VICTIM == p_cfg->u.value)
            {
                value = porttc_mb_en ? SYS_MONITOR_LOG_MODE_VICTIM_PORT_TC : SYS_MONITOR_LOG_MODE_VICTIM_PORT;
            }
            else if (SYS_MONITOR_LOG_MODE_ALL == p_cfg->u.value)
            {
                value = porttc_mb_en ? SYS_MONITOR_LOG_MODE_ALL_PORT_TC : SYS_MONITOR_LOG_MODE_ALL_PORT;
            }
            cmd = DRV_IOW(PreBufferRetrieveCtl_t, PreBufferRetrieveCtl_microburstMode_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));
        }
        else
        {
            cmd = DRV_IOW(EpeMiscLogCtl_t, EpeMiscLogCtl_microburstLogMode_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &(p_cfg->u.value)));
        }

        break;
    case  CTC_MONITOR_GLB_CONFIG_MBURST_THRD:
        CTC_MAX_VALUE_CHECK(p_cfg->u.mburst_thrd.level, MCHIP_CAP(SYS_CAP_MONITOR_LATENCY_MAX_LEVEL));
        /*CTC_ERROR_RETURN(_sys_usw_monitor_thrd_check(lchip, p_cfg->u.mburst_thrd.level, p_cfg->u.mburst_thrd.threshold,CTC_MONITOR_GLB_CONFIG_MBURST_THRD));*/
        p_usw_monitor_master[lchip]->mburst_thrd[p_cfg->u.mburst_thrd.level] = p_cfg->u.mburst_thrd.threshold;
        break;
    case  CTC_MONITOR_GLB_CONFIG_LANTENCY_MODE:
    case  CTC_MONITOR_GLB_CONFIG_BUFFER_SNAPSHOT_EN:
        {
            int32 ret = CTC_E_NONE;
            if(MCHIP_MON(lchip)->set_global_config)
            {
                ret = MCHIP_MON(lchip)->set_global_config(lchip, p_cfg);
            }
            else
            {
                ret = CTC_E_NOT_SUPPORT;
            }
            return ret;
        }
    case  CTC_MONITOR_GLB_CONFIG_QWM_EN:
        CTC_ERROR_RETURN(_sys_usw_monitor_set_queue_watermark_cfg(lchip, p_cfg));
        break;
    case CTC_MONITOR_GLB_CONFIG_MBURST_LOG_RATE:
        CTC_MAX_VALUE_CHECK(p_cfg->u.value, 15);
        value = (1 << p_cfg->u.value) - 1;
        cmd = DRV_IOW(EpeMiscLogCtl_t, EpeMiscLogCtl_microburstRandomThrd_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));
        break;
    case CTC_MONITOR_GLB_CONFIG_LATENCY_LOG_RATE:
        CTC_MAX_VALUE_CHECK(p_cfg->u.value, 15);
        value = (1 << p_cfg->u.value) - 1;
        cmd = DRV_IOW(EpeMiscLogCtl_t, EpeMiscLogCtl_latencyRandomThrd_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));
        break;
    default:
        return CTC_E_INVALID_PARAM;
    }

    return CTC_E_NONE;

}

int32
_sys_usw_monitor_get_global_config(uint8 lchip, ctc_monitor_glb_cfg_t* p_cfg)
{
    uint32 cmd = 0;
    uint32 field_val = 0;

    SYS_MONITOR_DBG_OUT(CTC_DEBUG_LEVEL_FUNC, "%s()\n", __FUNCTION__);
    //SYS_MONITOR_INIT_CHECK();
    CTC_PTR_VALID_CHECK(p_cfg);

    switch(p_cfg->cfg_type)
    {
    case  CTC_MONITOR_GLB_CONFIG_LATENCY_THRD:
        CTC_MAX_VALUE_CHECK(p_cfg->u.thrd.level, MCHIP_CAP(SYS_CAP_MONITOR_LATENCY_MAX_LEVEL));
        CTC_ERROR_RETURN(
            _sys_usw_monitor_get_thrd(lchip, CTC_MONITOR_LATENCY,0, p_cfg->u.thrd.level, &p_cfg->u.thrd.threshold, 0));
        p_cfg->u.thrd.threshold = p_cfg->u.thrd.threshold << 5;
        break;

    case  CTC_MONITOR_GLB_CONFIG_BUFFER_LOG_MODE:
        if (DRV_FROM_AT(lchip))
        {
            uint32 value = 0;

            cmd = DRV_IOR(PreBufferRetrieveCtl_t, PreBufferRetrieveCtl_microburstMode_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &value));

            if (SYS_MONITOR_LOG_MODE_VICTIM_PORT == value || SYS_MONITOR_LOG_MODE_VICTIM_PORT_TC == value)
            {
                p_cfg->u.value = SYS_MONITOR_LOG_MODE_VICTIM;
            }
            else if (SYS_MONITOR_LOG_MODE_ALL_PORT == value || SYS_MONITOR_LOG_MODE_ALL_PORT_TC == value)
            {
                p_cfg->u.value = SYS_MONITOR_LOG_MODE_ALL;
            }
            else
            {
                p_cfg->u.value = SYS_MONITOR_LOG_MODE_CAUSER;
            }
        }
        else
        {
            cmd = DRV_IOR(EpeMiscLogCtl_t, EpeMiscLogCtl_microburstLogMode_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &(p_cfg->u.value)));
        }
        break;
    case  CTC_MONITOR_GLB_CONFIG_MBURST_THRD:
        CTC_MAX_VALUE_CHECK(p_cfg->u.mburst_thrd.level, MCHIP_CAP(SYS_CAP_MONITOR_LATENCY_MAX_LEVEL));
        p_cfg->u.mburst_thrd.threshold = p_usw_monitor_master[lchip]->mburst_thrd[p_cfg->u.mburst_thrd.level];
        break;
    case  CTC_MONITOR_GLB_CONFIG_LANTENCY_MODE:
    case  CTC_MONITOR_GLB_CONFIG_BUFFER_SNAPSHOT_EN:
        if(MCHIP_MON(lchip)->get_global_config)
        {
            return MCHIP_MON(lchip)->get_global_config(lchip, p_cfg);
        }
        else
        {
            return CTC_E_NOT_SUPPORT;
        }
    case  CTC_MONITOR_GLB_CONFIG_QWM_EN:
        CTC_ERROR_RETURN(_sys_usw_monitor_get_queue_watermark_cfg(lchip, p_cfg));
        break;
    case CTC_MONITOR_GLB_CONFIG_MBURST_LOG_RATE:
        cmd = DRV_IOR(EpeMiscLogCtl_t, EpeMiscLogCtl_microburstRandomThrd_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        _sys_usw_monitor_mapping_log_thrd2shift(field_val+1, &p_cfg->u.value);
        break;
    case CTC_MONITOR_GLB_CONFIG_LATENCY_LOG_RATE:
        cmd = DRV_IOR(EpeMiscLogCtl_t, EpeMiscLogCtl_latencyRandomThrd_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        _sys_usw_monitor_mapping_log_thrd2shift(field_val+1, &p_cfg->u.value);
        break;
    default:
        return CTC_E_INVALID_PARAM;
    }

    return CTC_E_NONE;
}

int32
sys_usw_monitor_init_global(uint8 lchip, void * p_global_cfg)
{
    uint32 cmd = 0;
    uint32 field_val = 0;
    uint32 array_val[SYS_CHAN_BITMAP_IN_WORD] = {0};
    uint16 channel_id = 0;
    uint16 ptr_base = 0;
    uint8  dp_id = 0;
    ErmGlbMbCfg_m erm_glb_cfg;
    ErmResrcMonScanCtl_m erm_mon_ctl;
    IrmResrcMonScanCtl_m irm_mon_ctl;
    ds_t ds;

    /*EpePktProcCtl_latencyInformEn_f*/

    sal_memset(&erm_mon_ctl, 0 , sizeof(ErmResrcMonScanCtl_m));
    sal_memset(&irm_mon_ctl, 0 , sizeof(IrmResrcMonScanCtl_m));
    sal_memset(&erm_glb_cfg, 0 , sizeof(ErmGlbMbCfg_m));
    sal_memset(array_val,0,sizeof(array_val));
    cmd = DRV_IOR(ErmResrcMonScanCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &erm_mon_ctl));
    SetErmResrcMonScanCtl(A, resrcMonScanPushChannelEn_f, &erm_mon_ctl, array_val);
    SetErmResrcMonScanCtl(V, resrcMonScanEn_f, &erm_mon_ctl, 1);
    SetErmResrcMonScanCtl(V, resrcMonScanPushGroupDetailedEn_f, &erm_mon_ctl, 0);
    SetErmResrcMonScanCtl(V, resrcMonScanPushMiscEn_f, &erm_mon_ctl, 0);
    SetErmResrcMonScanCtl(V, resrcMonScanPushPortDetailedEn_f, &erm_mon_ctl, 0);
    SetErmResrcMonScanCtl(V, resrcMonScanPushScEn_f, &erm_mon_ctl, 0);
    /*TMM*/
    SetErmResrcMonScanCtl(A, resrcMonScanPushChannelScEn_f, &erm_mon_ctl, array_val);
    SetErmResrcMonScanCtl(V, resrcMonScanPushPortShadowEn_f, &erm_mon_ctl, 0);
    SetErmResrcMonScanCtl(V, resrcMonScanPushQueueDetailedEn_f, &erm_mon_ctl, 0);
    SetErmResrcMonScanCtl(V, resrcMonScanPushQueueShadowEn_f, &erm_mon_ctl, 0);
    /*TMG*/
    ptr_base = 0;
    SetErmResrcMonScanCtl(V, g_0_resrcMonPushPtrBase_f, &erm_mon_ctl, ptr_base); /* queue */
    ptr_base += MCHIP_CAP(SYS_CAP_QOS_QUEUE_NUM);
    SetErmResrcMonScanCtl(V, g_1_resrcMonPushPtrBase_f, &erm_mon_ctl, ptr_base); /* port sc */
    ptr_base += MCHIP_CAP(SYS_CAP_CHANNEL_NUM) * 4;
    SetErmResrcMonScanCtl(V, g_2_resrcMonPushPtrBase_f, &erm_mon_ctl, ptr_base); /* port */
    ptr_base += MCHIP_CAP(SYS_CAP_CHANNEL_NUM);
    SetErmResrcMonScanCtl(V, g_3_resrcMonPushPtrBase_f, &erm_mon_ctl, ptr_base); /* port shadow */
    ptr_base += MCHIP_CAP(SYS_CAP_CHANNEL_NUM);
    SetErmResrcMonScanCtl(V, g_4_resrcMonPushPtrBase_f, &erm_mon_ctl, ptr_base); /* queue detail */
    ptr_base += 32;
    SetErmResrcMonScanCtl(V, g_5_resrcMonPushPtrBase_f, &erm_mon_ctl, ptr_base); /* update sc */
    ptr_base += 2;
    SetErmResrcMonScanCtl(V, g_6_resrcMonPushPtrBase_f, &erm_mon_ctl, ptr_base); /* no use */

    cmd = DRV_IOW(ErmResrcMonScanCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &erm_mon_ctl));

    for(dp_id = 0; dp_id < MCHIP_CAP(SYS_CAP_DP_MAX_NUM); dp_id++)
    {
        cmd = DRV_IOR(IrmResrcMonScanCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, dp_id, cmd, &irm_mon_ctl));
        SetIrmResrcMonScanCtl(A, resrcMonScanPushChannelEn_f, &irm_mon_ctl, array_val);
        SetIrmResrcMonScanCtl(A, resrcMonScanPushChannelScEn_f, &irm_mon_ctl, array_val); /*TMM*/
        SetIrmResrcMonScanCtl(V, resrcMonScanEn_f, &irm_mon_ctl, 1);
        SetIrmResrcMonScanCtl(V, resrcMonScanPushMiscEn_f, &irm_mon_ctl, 0);
        SetIrmResrcMonScanCtl(V, resrcMonScanPushPortDetailedEn_f, &irm_mon_ctl, 0);
        SetIrmResrcMonScanCtl(V, resrcMonScanPushScEn_f, &irm_mon_ctl, 0);
        /*TMG per dp chan 0-127*/
        ptr_base = 0;
        SetIrmResrcMonScanCtl(V, g_0_resrcMonPushPtrBase_f, &irm_mon_ctl, ptr_base); /* port sc */
        ptr_base += MCHIP_CAP(SYS_CAP_CHANNEL_NUM) / MCHIP_CAP(SYS_CAP_DP_MAX_NUM) * 4;
        SetIrmResrcMonScanCtl(V, g_1_resrcMonPushPtrBase_f, &irm_mon_ctl, ptr_base); /* port */
        ptr_base += MCHIP_CAP(SYS_CAP_CHANNEL_NUM) * 2 / MCHIP_CAP(SYS_CAP_DP_MAX_NUM);
        SetIrmResrcMonScanCtl(V, g_2_resrcMonPushPtrBase_f, &irm_mon_ctl, ptr_base); /* TC */
        ptr_base += 8;
        SetIrmResrcMonScanCtl(V, g_3_resrcMonPushPtrBase_f, &irm_mon_ctl, ptr_base); /* SC */
        ptr_base += 4;
        SetIrmResrcMonScanCtl(V, g_4_resrcMonPushPtrBase_f, &irm_mon_ctl, ptr_base); /* misc */
        ptr_base += 2;
        SetIrmResrcMonScanCtl(V, g_5_resrcMonPushPtrBase_f, &irm_mon_ctl, ptr_base); /* no use */
        cmd = DRV_IOW(IrmResrcMonScanCtl_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, dp_id, cmd, &irm_mon_ctl));
    }

    /*AT*/
    cmd = DRV_IOR(ErmResrcStateInformScanCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
    SetErmResrcStateInformScanCtl(V, resrcStateInformScanChanVec_f, &ds, 0);
    SetErmResrcStateInformScanCtl(V, resrcStateInformScanEn_f, &ds, 1);
    SetErmResrcStateInformScanCtl(V, resrcStateInformScanPortEn_f, &ds, 1);
    SetErmResrcStateInformScanCtl(V, resrcStateInformScanPortScEn_f, &ds, 1);
    SetErmResrcStateInformScanCtl(V, resrcStateInformScanQueueEn_f, &ds, 1);
    cmd = DRV_IOW(ErmResrcStateInformScanCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));

    field_val = 0xFFFF;
    cmd = DRV_IOW(EpeMiscLogCtl_t, EpeMiscLogCtl_latencyRandomThrd_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
    cmd = DRV_IOW(EpeMiscLogCtl_t, EpeMiscLogCtl_microburstRandomThrd_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));

    field_val = 1;
    cmd = DRV_IOW(EpeMiscLogCtl_t, EpeMiscLogCtl_microburstLogMode_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));

    cmd = DRV_IOR(EpePktProcCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));
    SetEpePktProcCtl(V, latencyLogEn_f, &ds, 1);
    SetEpePktProcCtl(V, latencyDiscardEn_f, &ds, 1);
    SetEpePktProcCtl(V, latencyPrioMapEn_f, &ds, 0);
    SetEpePktProcCtl(V, latencyInformEn_f, &ds, 1);
    SetEpePktProcCtl(V, latencyCongestionEn_f, &ds, 1);
    cmd = DRV_IOW(EpePktProcCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &ds));

    cmd = DRV_IOW(LatencyMonScanCtl_t, LatencyMonScanCtl_scanEn_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));

    field_val = 0;
    cmd = DRV_IOW(EpeMiscLogCtl_t, EpeMiscLogCtl_microburstLogEn_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));

    CTC_ERROR_RETURN(_sys_usw_monitor_set_thrd(lchip, CTC_MONITOR_LATENCY, 0, 0, 0, 0));
    CTC_ERROR_RETURN(_sys_usw_monitor_set_thrd(lchip, CTC_MONITOR_LATENCY, 0, 1, 16, 0));
    CTC_ERROR_RETURN(_sys_usw_monitor_set_thrd(lchip, CTC_MONITOR_LATENCY, 0, 2, 64, 0));
    CTC_ERROR_RETURN(_sys_usw_monitor_set_thrd(lchip, CTC_MONITOR_LATENCY, 0, 3, 256, 0));
    CTC_ERROR_RETURN(_sys_usw_monitor_set_thrd(lchip, CTC_MONITOR_LATENCY, 0, 4, 1024, 0));
    CTC_ERROR_RETURN(_sys_usw_monitor_set_thrd(lchip, CTC_MONITOR_LATENCY, 0, 5, 4096, 0));
    CTC_ERROR_RETURN(_sys_usw_monitor_set_thrd(lchip, CTC_MONITOR_LATENCY, 0, 6, 16384, 0));
    CTC_ERROR_RETURN(_sys_usw_monitor_set_thrd(lchip, CTC_MONITOR_LATENCY, 0, 7, 65536, 0));
    field_val = 1;

    for(channel_id = 0; channel_id < MCHIP_CAP(SYS_CAP_MONITOR_MAX_CHANNEL); channel_id ++)
    {
        CTC_ERROR_RETURN(_sys_usw_monitor_set_thrd(lchip, CTC_MONITOR_BUFFER, CTC_MONITOR_BUFFER_PORT, 1,MCHIP_CAP(SYS_CAP_MONITOR_BUFFER_MAX_THRD), channel_id));
        cmd = DRV_IOR(DsDestChannel_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, channel_id, cmd, &ds));
        SetDsDestChannel(V, latencyActMonEn_f, &ds, 1);
        SetDsDestChannel(V, latencyWatermarkEn_f, &ds, 1);
        cmd = DRV_IOW(DsDestChannel_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, channel_id, cmd, &ds));
    }
    /* init mburst thrd value */
    p_usw_monitor_master[lchip]->mburst_thrd[1] = 2000;
    p_usw_monitor_master[lchip]->mburst_thrd[2] = 5000;
    p_usw_monitor_master[lchip]->mburst_thrd[3] = 20000;
    p_usw_monitor_master[lchip]->mburst_thrd[4] = 400000;
    p_usw_monitor_master[lchip]->mburst_thrd[5] = 1000000;
    p_usw_monitor_master[lchip]->mburst_thrd[6] = 5000000;
    p_usw_monitor_master[lchip]->mburst_thrd[7] = 10000000;

    cmd = DRV_IOR(ErmGlbMbCfg_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &erm_glb_cfg));
    SetErmGlbMbCfg(V, c2cMbMaxThrd_f, &erm_glb_cfg, MCHIP_CAP(SYS_CAP_MONITOR_BUFFER_MAX_THRD));
    SetErmGlbMbCfg(V, criticalMbMaxThrd_f, &erm_glb_cfg, MCHIP_CAP(SYS_CAP_MONITOR_BUFFER_MAX_THRD));
    SetErmGlbMbCfg(V, sc_0_scMbMaxThrd_f, &erm_glb_cfg, MCHIP_CAP(SYS_CAP_MONITOR_BUFFER_MAX_THRD));
    SetErmGlbMbCfg(V, sc_1_scMbMaxThrd_f, &erm_glb_cfg, MCHIP_CAP(SYS_CAP_MONITOR_BUFFER_MAX_THRD));
    SetErmGlbMbCfg(V, sc_2_scMbMaxThrd_f, &erm_glb_cfg, MCHIP_CAP(SYS_CAP_MONITOR_BUFFER_MAX_THRD));
    SetErmGlbMbCfg(V, sc_3_scMbMaxThrd_f, &erm_glb_cfg, MCHIP_CAP(SYS_CAP_MONITOR_BUFFER_MAX_THRD));
    SetErmGlbMbCfg(V, totalMbMaxThrd_f, &erm_glb_cfg, MCHIP_CAP(SYS_CAP_MONITOR_BUFFER_MAX_THRD));
    cmd = DRV_IOW(ErmGlbMbCfg_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &erm_glb_cfg));

    p_usw_monitor_master[lchip]->mb_thrd->c2c_thrd[1] = MCHIP_CAP(SYS_CAP_MONITOR_BUFFER_MAX_THRD);
    p_usw_monitor_master[lchip]->mb_thrd->critical_thrd[1] = MCHIP_CAP(SYS_CAP_MONITOR_BUFFER_MAX_THRD);
    p_usw_monitor_master[lchip]->mb_thrd->sc_thrd[0][1] = MCHIP_CAP(SYS_CAP_MONITOR_BUFFER_MAX_THRD);
    p_usw_monitor_master[lchip]->mb_thrd->sc_thrd[1][1] = MCHIP_CAP(SYS_CAP_MONITOR_BUFFER_MAX_THRD);
    p_usw_monitor_master[lchip]->mb_thrd->sc_thrd[2][1] = MCHIP_CAP(SYS_CAP_MONITOR_BUFFER_MAX_THRD);
    p_usw_monitor_master[lchip]->mb_thrd->sc_thrd[3][1] = MCHIP_CAP(SYS_CAP_MONITOR_BUFFER_MAX_THRD);
    p_usw_monitor_master[lchip]->mb_thrd->total_thrd[1] = MCHIP_CAP(SYS_CAP_MONITOR_BUFFER_MAX_THRD);

    return CTC_E_NONE;

}


int32
sys_usw_monitor_show_status(uint8 lchip)
{
    uint8 level = 0;
    uint32 threshold = 0;
    uint32 interval = 0;
    uint32 field_val = 0;
    uint32 cmd = 0;
    ctc_monitor_glb_cfg_t glb_cfg;

    SYS_MONITOR_INIT_CHECK();
    MONITOR_LOCK;

    SYS_MONITOR_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "----------------------------------------\n");
    SYS_MONITOR_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "Buffer Status:\n");
    SYS_MONITOR_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "----------------------------------------\n");
    CTC_ERROR_RETURN(sys_usw_monitor_get_timer(lchip, CTC_MONITOR_BUFFER, &interval));
    SYS_MONITOR_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "Scan intervel: %d<ms>\n", interval);
    if(DRV_FROM_AT(lchip))
    {
        IrmResrcMonState_m IrmRsc;
        cmd = DRV_IOR(IrmResrcMonState_t, DRV_ENTRY_FLAG);
        CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &IrmRsc));
        field_val = GetIrmResrcMonState(V, resrcShadowLock_f, &IrmRsc);
    }
    else if (DRV_FROM_TMM(lchip))
    {
        cmd = DRV_IOR(IrmMiscCtl_t, IrmMiscCtl_c2cCntLockEn_f);
        DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val);
    }
    SYS_MONITOR_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "Snapshot en  : %d\n", field_val);

    sal_memset(&glb_cfg, 0, sizeof(ctc_monitor_glb_cfg_t));
    glb_cfg.cfg_type = CTC_MONITOR_GLB_CONFIG_BUFFER_LOG_MODE;
    CTC_ERROR_RETURN(_sys_usw_monitor_get_global_config(lchip, &glb_cfg));

    if (glb_cfg.u.value == 0)
    {
        SYS_MONITOR_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "log mode     : causer");
    }
    else if (glb_cfg.u.value == 1)
    {
        SYS_MONITOR_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "log mode     : victim");
    }
    else
    {
        SYS_MONITOR_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "log mode     : all");
    }

    SYS_MONITOR_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "\n\n----------------------------------------\n");
    SYS_MONITOR_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "Latency Status:\n");
    SYS_MONITOR_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "----------------------------------------\n");
    CTC_ERROR_RETURN(sys_usw_monitor_get_timer(lchip, CTC_MONITOR_LATENCY, &interval));
    SYS_MONITOR_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "Scan intervel: %d<ms>\n", interval);

    if (DRV_FROM_TMM(lchip))
    {
        cmd = DRV_IOR(EpePktProcPathMonCtl_t, EpePktProcPathMonCtl_legacyFeatureEn_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        SYS_MONITOR_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "Legacy enable: %d\n", field_val);

        if(field_val)
        {
            field_val = CTC_MONITOR_LATENCY_MODE_0;
        }
        else
        {
            cmd = DRV_IOR(EpePktProcPathMonCtl_t, EpePktProcPathMonCtl_pathMonMode_f);
            CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));
        }
        SYS_MONITOR_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "Path mon mode: %d\n", field_val);
    }

    SYS_MONITOR_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "\n%-10s  %-10s\n", " latency level", "threshold");
    SYS_MONITOR_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "-------------------------\n");
    for (level = 0; level < 8; level++)
    {
        CTC_ERROR_RETURN(_sys_usw_monitor_get_thrd(lchip, CTC_MONITOR_LATENCY, 0,level, &threshold, 0));
        SYS_MONITOR_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "%-10d  %10"PRIu64"\n", level, ((uint64)threshold)<< 5);
    }
    SYS_MONITOR_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "\n%-10s  %-10s\n", " mburst level", "threshold");
    SYS_MONITOR_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "-------------------------\n");
    for (level = 0; level < 8; level++)
    {
        CTC_ERROR_RETURN(_sys_usw_monitor_get_thrd(lchip, CTC_MONITOR_MSG_MBURST_STATS, 0, level, &threshold, 0));
        SYS_MONITOR_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "%-10d  %10u\n", level, threshold);
    }
    MONITOR_UNLOCK;
    return CTC_E_NONE;
}

int32
sys_usw_monitor_show_path(uint8 lchip)
{
    int32 ret = CTC_E_NONE;
    SYS_MONITOR_INIT_CHECK();
    MONITOR_LOCK;
    if (MCHIP_MON(lchip)->show_path)
    {
        ret = MCHIP_MON(lchip)->show_path(lchip);
    }
    MONITOR_UNLOCK;
    return ret;
}

int32
sys_usw_monitor_clear_stats(uint8 lchip,  uint32 gport)
{
    uint32 channel_id = 0;
    uint16 lport = 0;
    uint8 i = 0;
    sys_usw_dmps_port_info_t dmps_port_info = {0};

    SYS_MONITOR_INIT_CHECK();
    
    SYS_MAP_CTC_GPORT_TO_DRV_LPORT_WITH_CHECK(gport, lchip, lport);
    dmps_port_info.gport = gport;
    CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_CHAN_ID, &channel_id));
    if (channel_id >= MCHIP_CAP(SYS_CAP_MONITOR_MAX_CHANNEL))
    {
        return CTC_E_INVALID_PARAM;
    }
    MONITOR_LOCK;
    p_usw_monitor_master[lchip]->buffer_stats[channel_id][0] = 0;
    p_usw_monitor_master[lchip]->buffer_stats[channel_id][1] = 0;

    for (i = 0; i < 8; i++)
    {
        p_usw_monitor_master[lchip]->latency_stats[channel_id][i] = 0;
    }
    MONITOR_UNLOCK;

    return CTC_E_NONE;
}


int32
sys_usw_monitor_show_stats(uint8 lchip, uint32 gport)
{
    uint8 i = 0;
    uint32 channel_id = 0;
    uint16 lport = 0;
    sys_usw_dmps_port_info_t dmps_port_info = {0};
    char *buffer[2] = {"unicat", "mcast"};
    char *latecny[8] = {"zone0", "zone1", "zone2", "zone3", "zone4", "zone5", "zone6", "zone7"};

    SYS_MONITOR_INIT_CHECK();
    SYS_MAP_CTC_GPORT_TO_DRV_LPORT_WITH_CHECK(gport, lchip, lport);
    dmps_port_info.gport = gport;
    CTC_ERROR_RETURN(sys_usw_port_api_get_dmps_property(lchip, &dmps_port_info, SYS_PORT_API_DMPS_PROP_CHAN_ID, &channel_id));
    if (channel_id >= MCHIP_CAP(SYS_CAP_MONITOR_MAX_CHANNEL))
    {
        return CTC_E_INVALID_PARAM;
    }
    MONITOR_LOCK;
    SYS_MONITOR_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "%-15s %-10s\n", "BUFFER", "COUNT");
    SYS_MONITOR_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "------------------------------\n");
    for (i = 0; i < 2; i++)
    {
        SYS_MONITOR_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "%-15s :%u\n", buffer[i],
                            p_usw_monitor_master[lchip]->buffer_stats[channel_id][i]);
    }

    SYS_MONITOR_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "\n%-15s %-10s\n", "LATENCY", "COUNT");
    SYS_MONITOR_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "------------------------------\n");
    for (i = 0; i < 8; i++)
    {
        SYS_MONITOR_DBG_OUT(CTC_DEBUG_LEVEL_DUMP, "%-15s :%"PRIu64"\n", latecny[i],
                            p_usw_monitor_master[lchip]->latency_stats[channel_id][i]);
    }
    MONITOR_UNLOCK;

    return CTC_E_NONE;
}


int32
sys_usw_monitor_testing_en(uint8 lchip, bool enable)
{
    #if 0
    uint32 cmd = 0;
    uint32 field_val = 0;
    uint32 value[4];
    ds_t ds;
    uint32 channel_id = 0;
	uint8 i = 0;

	field_val = enable?1:0;

	for(i=0;i<4;i++)
	{
		value[i] = enable?0xFFFFFFFF:0;
	}

    cmd = DRV_IOW(QMgrEnqCtl_t, QMgrEnqCtl_activeBufMonEn_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));

    cmd = DRV_IOW(QMgrEnqCtl_t, QMgrEnqCtl_microBurstInformEn_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));

    cmd = DRV_IOW(QMgrEnqCtl_t, QMgrEnqCtl_activeBufMonTcEn_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));

    cmd = DRV_IOW(QMgrEnqCtl_t, QMgrEnqCtl_activeBufMonTotalEn_f);
    CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, 0, cmd, &field_val));

    cmd = DRV_IOR(QMgrEnqCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
    SetQMgrEnqCtl(A,  activeBufMonChanEn_f, ds, value);
    cmd = DRV_IOW(QMgrEnqCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));


    cmd = DRV_IOR(LatencyMonScanCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));
    SetLatencyMonScanCtl(A,  reportEn_f, ds, value);
    cmd = DRV_IOW(LatencyMonScanCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, ds));

    cmd = DRV_IOR(LatencyMonScanCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 1, cmd, ds));
    SetLatencyMonScanCtl(A,  reportEn_f, ds, value);
    cmd = DRV_IOW(LatencyMonScanCtl_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 1, cmd, ds));

    for (channel_id = 0; channel_id < 128; channel_id++)
    {
        cmd = DRV_IOW(DsDestChannel_t, DsDestChannel_latencyActMonEn_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, channel_id, cmd, &field_val));
        cmd = DRV_IOW(DsDestChannel_t, DsDestChannel_latencyInformEn_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, channel_id, cmd, &field_val));
        cmd = DRV_IOW(DsDestChannel_t, DsDestChannel_latencyWatermarkEn_f);
        CTC_ERROR_RETURN(DRV_FIELD_IOCTL(lchip, channel_id, cmd, &field_val));
    }
    #endif
    return 0;

}

void
sys_usw_monitor_buffer_process_isr(uint8 index, ctc_monitor_msg_t *p_msg)
{
    uint8 i = 0;
    char* monitor_str[2] = {"B","L"};
    char* msg_str[3] = {"E","S","MB"};
#ifdef CTC_SHELL_DEBUG_ON
    uint8 lchip = 0;
    sys_usw_get_local_chip_id(p_msg->gchip, &lchip);
#endif
    if (p_msg->msg_type == CTC_MONITOR_MSG_EVENT)
    {
        SYS_MONITOR_DBG_OUT(CTC_DEBUG_LEVEL_EXPORT, "No.%-4d %-4s%"PRIu64"  %s%s  %s%d",
                      index,
                      "TS:", p_msg->timestamp,
                      monitor_str[p_msg->monitor_type],
                      msg_str[p_msg->msg_type],
                      "gchip:", p_msg->gchip);
        if(p_msg->u.buffer_event.buffer_type == CTC_MONITOR_BUFFER_PORT)
        {
            SYS_MONITOR_DBG_OUT(CTC_DEBUG_LEVEL_EXPORT, " %8s%04x %8s%-8u %8s%-8u %8s%-8d %8s%-8d\n",
                      "Gport:0x", p_msg->u.buffer_event.gport,
                       "UcCnt:", p_msg->u.buffer_event.uc_cnt,
                       "McCnt:", p_msg->u.buffer_event.mc_cnt,
                       "State:", p_msg->u.buffer_event.event_state,
                       "CngLevel:", p_msg->u.buffer_event.threshold_level);
        }
        else if(p_msg->u.buffer_event.buffer_type == CTC_MONITOR_BUFFER_TOTAL)
        {
            SYS_MONITOR_DBG_OUT(CTC_DEBUG_LEVEL_EXPORT, " %8s%-8u %8s%-8d\n",
                       "TotalCnt:", p_msg->u.buffer_event.buffer_cnt,
                       "State:", p_msg->u.buffer_event.event_state);
        }
        else if(p_msg->u.buffer_event.buffer_type == CTC_MONITOR_BUFFER_SC)
        {
            SYS_MONITOR_DBG_OUT(CTC_DEBUG_LEVEL_EXPORT, " %8s%-8d %8s%-8u %8s%-8d\n",
                       "SC:",p_msg->u.buffer_event.sc,
                       "ScCnt:",p_msg->u.buffer_event.buffer_cnt,
                       "State:",p_msg->u.buffer_event.event_state);
        }
        else if(p_msg->u.buffer_event.buffer_type == CTC_MONITOR_BUFFER_C2C)
        {
            SYS_MONITOR_DBG_OUT(CTC_DEBUG_LEVEL_EXPORT, " %8s%-8u %8s%-8d\n",
                       "C2cCnt:", p_msg->u.buffer_event.buffer_cnt,
                       "State:", p_msg->u.buffer_event.event_state);
        }
        else if(p_msg->u.buffer_event.buffer_type == CTC_MONITOR_BUFFER_PORT_PRIO_CLASS)
        {
            SYS_MONITOR_DBG_OUT(CTC_DEBUG_LEVEL_EXPORT, " %8s%04x %8s%-8d %8s%-8u %8s%-8u %8s%-8d\n",
                       "Gport:0x", p_msg->u.buffer_event.gport,
                       "PrioClass:", p_msg->u.buffer_event.sc,
                       "UcCnt:", p_msg->u.buffer_event.uc_cnt,
                       "McCnt:", p_msg->u.buffer_event.mc_cnt,
                       "State:", p_msg->u.buffer_event.event_state);
        }
    }
    else if (p_msg->msg_type == CTC_MONITOR_MSG_STATS)
    {
        if(p_msg->u.buffer_stats.dir == CTC_EGRESS)
        {
            if (p_msg->u.buffer_stats.buffer_type == CTC_MONITOR_BUFFER_PORT)
            {
                SYS_MONITOR_DBG_OUT(CTC_DEBUG_LEVEL_EXPORT, "No.%-4d %-4s%"PRIu64"  %8s%s  %s%d %8s %8s%04x %8s%-8u %8s%-8u %8s%-8u %6s%-2u\n",
                          index,
                          "TS:", p_msg->timestamp,
                          monitor_str[p_msg->monitor_type],
                          msg_str[p_msg->msg_type],
                          "gchip:", p_msg->gchip,
                          "EGRESS",
                          "Gport:0x", p_msg->u.buffer_stats.gport,
                          "PktCnt:", p_msg->u.buffer_stats.buffer_cnt,
                          "UcCnt:", p_msg->u.buffer_stats.uc_cnt,
                          "McCnt:", p_msg->u.buffer_stats.non_uc_cnt,
                          "ppId:", p_msg->pp_id);
            }
            else if(p_msg->u.buffer_stats.buffer_type == CTC_MONITOR_BUFFER_SC)
            {
                SYS_MONITOR_DBG_OUT(CTC_DEBUG_LEVEL_EXPORT, "No.%-4d %-4s%"PRIu64"  %8s%s  %s%d %8s %8s%-8d %8s%-8u %8s%-8u %8s%-8u %6s%-2u\n",
                          index,
                          "TS:", p_msg->timestamp,
                          monitor_str[p_msg->monitor_type],
                          msg_str[p_msg->msg_type],
                          "gchip:", p_msg->gchip,
                          "EGRESS",
                          "SC:",p_msg->u.buffer_stats.sc,
                          "ScCnt:", p_msg->u.buffer_stats.buffer_cnt,
                          "UcCnt:", p_msg->u.buffer_stats.uc_cnt,
                          "McCnt:", p_msg->u.buffer_stats.non_uc_cnt,
                          "ppId:", p_msg->pp_id);
            }
            else if(p_msg->u.buffer_stats.buffer_type == CTC_MONITOR_BUFFER_TOTAL)
            {
                SYS_MONITOR_DBG_OUT(CTC_DEBUG_LEVEL_EXPORT, "No.%-4d %-4s%"PRIu64"  %8s%s  %s%d %8s %8s%-8u %8s%-8u %8s%-8u %6s%-2u\n",
                          index,
                          "TS:", p_msg->timestamp,
                          monitor_str[p_msg->monitor_type],
                          msg_str[p_msg->msg_type],
                          "gchip:", p_msg->gchip,
                          "EGRESS",
                          "Total:", p_msg->u.buffer_stats.buffer_cnt,
                          "UcCnt:", p_msg->u.buffer_stats.uc_cnt,
                          "McCnt:", p_msg->u.buffer_stats.non_uc_cnt,
                          "ppId:", p_msg->pp_id);
            }
            else if(p_msg->u.buffer_stats.buffer_type == CTC_MONITOR_BUFFER_QUEUE)
            {
                SYS_MONITOR_DBG_OUT(CTC_DEBUG_LEVEL_EXPORT, "No.%-4d %-4s%"PRIu64"  %8s%s  %s%d %8s %8s%04x %8s %8s%-8d%8s%-8u %8s%-8u %8s%-8u %6s%-2u\n",
                          index,
                          "TS:", p_msg->timestamp,
                          monitor_str[p_msg->monitor_type],
                          msg_str[p_msg->msg_type],
                          "gchip:", p_msg->gchip,
                          "EGRESS",
                          "Gport:0x", p_msg->u.buffer_stats.queue_id.gport,
                          "Queue Type:NETWORK_EGRESS",
                          "Queue ID:", p_msg->u.buffer_stats.queue_id.queue_id,
                          "Queue cnt:", p_msg->u.buffer_stats.buffer_cnt,
                          "UcCnt:", p_msg->u.buffer_stats.uc_cnt,
                          "McCnt:", p_msg->u.buffer_stats.non_uc_cnt,
                          "ppId:", p_msg->pp_id);
            }
            else if(p_msg->u.buffer_stats.buffer_type == CTC_MONITOR_BUFFER_PORT_SC)
            {
                SYS_MONITOR_DBG_OUT(CTC_DEBUG_LEVEL_EXPORT, "No.%-4d %-4s%"PRIu64"  %8s%s %8s %8s%04x %8s%-8d %8s%-8u %8s%-8u %6s%-2u\n",
                          index,
                          "TS:", p_msg->timestamp,
                          monitor_str[p_msg->monitor_type],
                          msg_str[p_msg->msg_type],
                          "EGRESS",
                          "Gport:0x", p_msg->u.buffer_stats.gport,
                          "PortSc Cnt:", p_msg->u.buffer_stats.buffer_cnt,
                          "UcCnt:", p_msg->u.buffer_stats.uc_cnt,
                          "McCnt:", p_msg->u.buffer_stats.non_uc_cnt,
                          "ppId:", p_msg->pp_id);
            }
            else if(p_msg->u.buffer_stats.buffer_type == CTC_MONITOR_BUFFER_PORT_PRIO_CLASS)
            {
                SYS_MONITOR_DBG_OUT(CTC_DEBUG_LEVEL_EXPORT, "No.%-4d %-4s%"PRIu64"  %8s%s %8s %8s%04x %8s%-8d %8s%-8u %8s%-8u %11s%-2u %6s%-2u\n",
                          index,
                          "TS:", p_msg->timestamp,
                          monitor_str[p_msg->monitor_type],
                          msg_str[p_msg->msg_type],
                          "INGRESS",
                          "Gport:0x", p_msg->u.buffer_stats.gport,
                          "PortPrioClass Cnt:", p_msg->u.buffer_stats.buffer_cnt,
                          "UcCnt:", p_msg->u.buffer_stats.uc_cnt,
                          "McCnt:", p_msg->u.buffer_stats.non_uc_cnt,
                          "PrioClass:", p_msg->u.buffer_stats.sc,
                          "ppId:", p_msg->pp_id);
            }
        }
        else if (p_msg->u.buffer_stats.dir == CTC_INGRESS)
        {
            if (p_msg->u.buffer_stats.buffer_type == CTC_MONITOR_BUFFER_PORT)
            {
                SYS_MONITOR_DBG_OUT(CTC_DEBUG_LEVEL_EXPORT, "No.%-4d %-4s%"PRIu64"  %8s%s  %s%d %8s %8s%04x %8s%-8u %8s%-8u %8s%-8u %6s%-2u\n",
                          index,
                          "TS:", p_msg->timestamp,
                          monitor_str[p_msg->monitor_type],
                          msg_str[p_msg->msg_type],
                          "gchip:", p_msg->gchip,
                          "INGRESS",
                          "Gport:0x", p_msg->u.buffer_stats.gport,
                          "PktCnt:", p_msg->u.buffer_stats.buffer_cnt,
                          "UcCnt:", p_msg->u.buffer_stats.uc_cnt,
                          "McCnt:", p_msg->u.buffer_stats.non_uc_cnt,
                          "ppId:", p_msg->pp_id);
            }
            else if(p_msg->u.buffer_stats.buffer_type == CTC_MONITOR_BUFFER_SC)
            {
                SYS_MONITOR_DBG_OUT(CTC_DEBUG_LEVEL_EXPORT, "No.%-4d %-4s%"PRIu64"  %8s%s  %s%d %8s %8s%-8d %8s%-8u %8s%-8u %8s%-8u %6s%-2u\n",
                          index,
                          "TS:", p_msg->timestamp,
                          monitor_str[p_msg->monitor_type],
                          msg_str[p_msg->msg_type],
                          "gchip:", p_msg->gchip,
                          "INGRESS",
                          "SC:",p_msg->u.buffer_stats.sc,
                          "ScCnt:", p_msg->u.buffer_stats.buffer_cnt,
                          "UcCnt:", p_msg->u.buffer_stats.uc_cnt,
                          "McCnt:", p_msg->u.buffer_stats.non_uc_cnt,
                          "ppId:", p_msg->pp_id);
            }
            else if(p_msg->u.buffer_stats.buffer_type == CTC_MONITOR_BUFFER_TOTAL)
            {
                SYS_MONITOR_DBG_OUT(CTC_DEBUG_LEVEL_EXPORT, "No.%-4d %-4s%"PRIu64"  %8s%s  %s%d %8s %8s%-8u %8s%-8u %8s%-8u %6s%-2u\n",
                          index,
                          "TS:", p_msg->timestamp,
                          monitor_str[p_msg->monitor_type],
                          msg_str[p_msg->msg_type],
                          "gchip:", p_msg->gchip,
                          "INGRESS",
                          "Total:", p_msg->u.buffer_stats.buffer_cnt,
                          "UcCnt:", p_msg->u.buffer_stats.uc_cnt,
                          "McCnt:", p_msg->u.buffer_stats.non_uc_cnt,
                          "ppId:", p_msg->pp_id);
            }
            else if(p_msg->u.buffer_stats.buffer_type == CTC_MONITOR_BUFFER_PORT_SC)
            {
                SYS_MONITOR_DBG_OUT(CTC_DEBUG_LEVEL_EXPORT, "No.%-4d %-4s%"PRIu64"  %8s%s %8s %8s%04x %8s%-8d %8s%-8u %8s%-8u %6s%-2u\n",
                          index,
                          "TS:", p_msg->timestamp,
                          monitor_str[p_msg->monitor_type],
                          msg_str[p_msg->msg_type],
                          "INGRESS",
                          "Gport:0x", p_msg->u.buffer_stats.gport,
                          "PortSc Cnt:", p_msg->u.buffer_stats.buffer_cnt,
                          "UcCnt:", p_msg->u.buffer_stats.uc_cnt,
                          "McCnt:", p_msg->u.buffer_stats.non_uc_cnt,
                          "ppId:", p_msg->pp_id);
            }
            else if(p_msg->u.buffer_stats.buffer_type == CTC_MONITOR_BUFFER_PORT_PRIO_CLASS)
            {
                SYS_MONITOR_DBG_OUT(CTC_DEBUG_LEVEL_EXPORT, "No.%-4d %-4s%"PRIu64"  %8s%s %8s %8s%04x %8s%-8d %8s%-8u %8s%-8u %11s%-2u %6s%-2u\n",
                          index,
                          "TS:", p_msg->timestamp,
                          monitor_str[p_msg->monitor_type],
                          msg_str[p_msg->msg_type],
                          "INGRESS",
                          "Gport:0x", p_msg->u.buffer_stats.gport,
                          "PortPrioClass Cnt:", p_msg->u.buffer_stats.buffer_cnt,
                          "UcCnt:", p_msg->u.buffer_stats.uc_cnt,
                          "McCnt:", p_msg->u.buffer_stats.non_uc_cnt,
                          "PrioClass:", p_msg->u.buffer_stats.sc,
                          "ppId:", p_msg->pp_id);
            } 
        }
    }
    else if (p_msg->msg_type == CTC_MONITOR_MSG_MBURST_STATS)
    {
        SYS_MONITOR_DBG_OUT(CTC_DEBUG_LEVEL_EXPORT, "No.%-4d %-4s%"PRIu64"  %s%s  %s%d %8s%04x %8s",
                  index,
                  "TS:", p_msg->timestamp,
                  monitor_str[p_msg->monitor_type],
                  msg_str[p_msg->msg_type],
                  "gchip:", p_msg->gchip,
                  "Gport:0x", p_msg->u.mburst_stats.gport,
                  "thrd cnt:");
    
        for (i = 0; i < 8; i++)
        {
            SYS_MONITOR_DBG_OUT(CTC_DEBUG_LEVEL_EXPORT, " %8u",  p_msg->u.mburst_stats.threshold_cnt[i]);
        }
        SYS_MONITOR_DBG_OUT(CTC_DEBUG_LEVEL_EXPORT, " \n");
    }
}

void
sys_usw_monitor_latency_process_isr(uint8 index, ctc_monitor_msg_t *p_msg)
{
    char* monitor_str[2] = {"B","L"};
    char* msg_str[3] = {"E","S","MB"};
#ifdef CTC_SHELL_DEBUG_ON
    uint8 lchip = 0;
    sys_usw_get_local_chip_id(p_msg->gchip, &lchip);
#endif
    if (p_msg->msg_type == CTC_MONITOR_MSG_EVENT)
    {
        SYS_MONITOR_DBG_OUT(CTC_DEBUG_LEVEL_EXPORT, "No.%-4d %s%-20"PRIu64" %s%s %s%d %s%04x %s%04x %s%d %s%-20"PRIu64" %s%d %s%04x\n",
                  index,
                  "TS:",p_msg->timestamp,
                  monitor_str[p_msg->monitor_type],
                  msg_str[p_msg->msg_type],
                  "Gchip:", p_msg->gchip,
                  "Gport:0x", p_msg->u.latency_event.gport,
                  "SrcPort:0x", p_msg->u.latency_event.source_port,
                  "State:", p_msg->u.latency_event.event_state,
                  "Latency:", p_msg->u.latency_event.latency,
                  "Level:", p_msg->u.latency_event.level,
                  "port:0x", p_msg->u.latency_event.port);
    }
    else if (p_msg->msg_type == CTC_MONITOR_MSG_STATS)
    {
        SYS_MONITOR_DBG_OUT(CTC_DEBUG_LEVEL_EXPORT, "No.%-4d %-s%20"PRIu64" %s%s %s%d %s%04x %s%12u%12u%12u%12u%12u%12u%12u%12u\n",
                index,
                "TS:",p_msg->timestamp,
                monitor_str[p_msg->monitor_type],
                msg_str[p_msg->msg_type],
                "Gchip:", p_msg->gchip,
                "Gport:0x",p_msg->u.latency_stats.gport,
                "Thrd:",p_msg->u.latency_stats.threshold_cnt[0],
                p_msg->u.latency_stats.threshold_cnt[1],
                p_msg->u.latency_stats.threshold_cnt[2],
                p_msg->u.latency_stats.threshold_cnt[3],
                p_msg->u.latency_stats.threshold_cnt[4],
                p_msg->u.latency_stats.threshold_cnt[5],
                p_msg->u.latency_stats.threshold_cnt[6],
                p_msg->u.latency_stats.threshold_cnt[7]);
    }
}

void
sys_usw_monitor_process_isr(ctc_monitor_data_t * info, void* userdata)
{
    uint16 index = 0;
    ctc_monitor_msg_t *p_msg = NULL;
#ifdef CTC_SHELL_DEBUG_ON
    uint8 lchip = 0;
#endif
    if (info == NULL)
    {
        return;
    }
#ifdef CTC_SHELL_DEBUG_ON
    sys_usw_get_local_chip_id(info[0].p_msg->gchip, &lchip);
#endif
    SYS_MONITOR_DBG_OUT(CTC_DEBUG_LEVEL_EXPORT,"-------------------------<B,L>: Buffer, Latency <E,S>:Event,Stats---------------------------------\n");

    for (index = 0; index < info->msg_num; index++)
    {
        p_msg = &info->p_msg[index];

        if (p_msg->monitor_type == CTC_MONITOR_LATENCY)
        {
            sys_usw_monitor_latency_process_isr(index, p_msg);
        }
        else if (p_msg->monitor_type == CTC_MONITOR_BUFFER)
        {
            sys_usw_monitor_buffer_process_isr(index, p_msg);
        } 
    }

    SYS_MONITOR_DBG_OUT(CTC_DEBUG_LEVEL_EXPORT, "-------------------------------------------------------------------------------------\n");

    return;
}
#define ______MONITOR_API______
int32
sys_usw_monitor_set_config(uint8 lchip, ctc_monitor_config_t *p_cfg)
{
    int32 ret = CTC_E_NONE;
    SYS_MONITOR_INIT_CHECK();

    MONITOR_LOCK;
    ret = _sys_usw_monitor_set_config(lchip, p_cfg);
    MONITOR_UNLOCK;
    return ret;
}

int32
sys_usw_monitor_get_config(uint8 lchip, ctc_monitor_config_t *p_cfg)
{
    int32 ret = CTC_E_NONE;
    SYS_MONITOR_INIT_CHECK();

    MONITOR_LOCK;
    ret = _sys_usw_monitor_get_config(lchip, p_cfg);
    MONITOR_UNLOCK;
    return ret;
}

int32
sys_usw_monitor_set_config2(uint8 lchip, ctc_monitor_config_type_t type, void* p_cfg)
{
    int32 ret = CTC_E_NONE;
    SYS_MONITOR_INIT_CHECK();

    MONITOR_LOCK;
    ret = _sys_usw_monitor_set_config2(lchip, type, p_cfg);
    MONITOR_UNLOCK;
    return ret;
}

int32
sys_usw_monitor_get_config2(uint8 lchip, ctc_monitor_config_type_t type, void* p_cfg)
{
    int32 ret = CTC_E_NONE;
    SYS_MONITOR_INIT_CHECK();

    MONITOR_LOCK;
    ret = _sys_usw_monitor_get_config2(lchip, type, p_cfg);
    MONITOR_UNLOCK;
    return ret;
}
int32
sys_usw_monitor_get_watermark(uint8 lchip, ctc_monitor_watermark_t *p_watermark)
{
    int32 ret = CTC_E_NONE;
    SYS_MONITOR_INIT_CHECK();

    MONITOR_LOCK;
    ret = _sys_usw_monitor_get_watermark(lchip, p_watermark);
    MONITOR_UNLOCK;
    return ret;
}

int32
sys_usw_monitor_clear_watermark(uint8 lchip, ctc_monitor_watermark_t *p_watermark)
{
    int32 ret = CTC_E_NONE;
    SYS_MONITOR_INIT_CHECK();

    MONITOR_LOCK;
    ret = _sys_usw_monitor_clear_watermark(lchip, p_watermark);
    MONITOR_UNLOCK;
    return ret;
}

int32
sys_usw_monitor_set_global_config(uint8 lchip, ctc_monitor_glb_cfg_t* p_cfg)
{
    int32 ret = CTC_E_NONE;
    SYS_MONITOR_INIT_CHECK();

    MONITOR_LOCK;
    ret = _sys_usw_monitor_set_global_config(lchip, p_cfg);
    MONITOR_UNLOCK;
    return ret;
}

int32
sys_usw_monitor_get_global_config(uint8 lchip, ctc_monitor_glb_cfg_t* p_cfg)
{
    int32 ret = CTC_E_NONE;
    SYS_MONITOR_INIT_CHECK();

    MONITOR_LOCK;
    ret = _sys_usw_monitor_get_global_config(lchip, p_cfg);
    MONITOR_UNLOCK;
    return ret;
}

#define ______MONITOR_WB______
STATIC int32
_sys_usw_monitor_path_wb_sync_func(void* data, void* user_data)
{
    uint32 max_entry_cnt = 0;
    sys_monitor_path_config_t *p_path_lat = (sys_monitor_path_config_t *)data;
    sys_wb_monitor_path_latency_t *p_wb_path_lat;
    sys_traverse_t *traversal_data = (sys_traverse_t *)user_data;
    ctc_wb_data_t *wb_data = (ctc_wb_data_t *)traversal_data->data;

    max_entry_cnt = wb_data->buffer_len/ (wb_data->key_len + wb_data->data_len);
    p_wb_path_lat = (sys_wb_monitor_path_latency_t *)wb_data->buffer + wb_data->valid_cnt;

    p_wb_path_lat->src_lport = p_path_lat->src_lport;
    p_wb_path_lat->dst_lport = p_path_lat->dst_lport;
    if (++wb_data->valid_cnt == max_entry_cnt)
    {
        CTC_ERROR_RETURN(ctc_wb_add_entry(wb_data));
        wb_data->valid_cnt = 0;
    }

    return CTC_E_NONE;
}

STATIC int32
_sys_usw_monitor_wb_sync(uint8 lchip,uint32 app_id)
{
    int32 ret = CTC_E_NONE;
    ctc_wb_data_t wb_data = {0};
    sys_traverse_t user_data = {0};
    sys_wb_monitor_master_t* wb_monitor_master = NULL;
    sys_wb_monitor_buf_scan_ctl_t* wb_monitor_buf_scan = NULL;

    if(!DRV_FROM_TMM(lchip))
    {
        return CTC_E_NONE;
    }

     CTC_WB_ALLOC_BUFFER(&wb_data.buffer);
    MONITOR_LOCK;
    /*syncup matser*/
    if (app_id == 0 || CTC_WB_SUBID(app_id) == SYS_WB_APPID_MONITOR_SUBID_MASTER)
    {
        CTC_WB_INIT_DATA_T((&wb_data), sys_wb_monitor_master_t, CTC_FEATURE_MONITOR, SYS_WB_APPID_MONITOR_SUBID_MASTER);

        wb_monitor_master = (sys_wb_monitor_master_t *)wb_data.buffer;
        sal_memset(wb_monitor_master, 0, sizeof(sys_wb_monitor_master_t));
        wb_monitor_master->lchip = lchip;
        wb_monitor_master->version = SYS_WB_VERSION_MONITOR;
        sal_memcpy(wb_monitor_master->port_array[0], p_usw_monitor_master[lchip]->port_array[0], sizeof(wb_monitor_master->port_array[0]));
        sal_memcpy(wb_monitor_master->port_array[1], p_usw_monitor_master[lchip]->port_array[1], sizeof(wb_monitor_master->port_array[1]));
        if (DRV_FROM_AT(lchip))
        {
            wb_monitor_master->total_en_igs = p_usw_monitor_master[lchip]->buf_scan->total_en_igs;
            wb_monitor_master->total_en_egs = p_usw_monitor_master[lchip]->buf_scan->total_en_egs;
            wb_monitor_master->sc_en_igs = p_usw_monitor_master[lchip]->buf_scan->sc_en_igs;
            wb_monitor_master->sc_en_egs = p_usw_monitor_master[lchip]->buf_scan->sc_en_egs;
            wb_monitor_master->c2c_en_igs = p_usw_monitor_master[lchip]->buf_scan->c2c_en_igs;
            wb_monitor_master->c2c_en_egs = p_usw_monitor_master[lchip]->buf_scan->c2c_en_egs;
            wb_monitor_master->critical_en_igs = p_usw_monitor_master[lchip]->buf_scan->critical_en_igs;
            wb_monitor_master->critical_en_egs = p_usw_monitor_master[lchip]->buf_scan->critical_en_egs;
            wb_monitor_master->round_trip_en = p_usw_monitor_master[lchip]->buf_scan->round_trip_en;
            wb_monitor_master->span_en = p_usw_monitor_master[lchip]->buf_scan->span_en;
        }
        wb_data.valid_cnt = 1;
        CTC_ERROR_GOTO(ctc_wb_add_entry(&wb_data), ret, done);
        CTC_WB_SYNC_END_DATA(CTC_FEATURE_MONITOR, SYS_WB_APPID_MONITOR_SUBID_MASTER);
    }

    /*syncup buf_scan*/
    if (DRV_FROM_AT(lchip) && (app_id == 0 || CTC_WB_SUBID(app_id) == SYS_WB_APPID_MONITOR_SUBID_BUFF_SCAN_CTL))
    {
        uint16 lport = 0;
        CTC_WB_INIT_DATA_T((&wb_data), sys_wb_monitor_buf_scan_ctl_t, CTC_FEATURE_MONITOR, SYS_WB_APPID_MONITOR_SUBID_BUFF_SCAN_CTL);

        for (lport = 0; lport < MAX_PORT_NUM_PER_CHIP; lport++)
        {
            wb_monitor_buf_scan = (sys_wb_monitor_buf_scan_ctl_t *)wb_data.buffer;
            sal_memset(wb_monitor_buf_scan, 0, sizeof(sys_wb_monitor_buf_scan_ctl_t));
            wb_monitor_buf_scan->lport = lport;
            wb_monitor_buf_scan->port_sc_en_igs = p_usw_monitor_master[lchip]->buf_scan->port[lport].port_sc_en_igs;
            wb_monitor_buf_scan->port_sc_en_egs = p_usw_monitor_master[lchip]->buf_scan->port[lport].port_sc_en_egs;
            wb_monitor_buf_scan->port_tc_en_igs = p_usw_monitor_master[lchip]->buf_scan->port[lport].port_tc_en_igs;
            wb_monitor_buf_scan->port_tc_en_egs = p_usw_monitor_master[lchip]->buf_scan->port[lport].port_tc_en_egs;
            wb_monitor_buf_scan->queue_en = p_usw_monitor_master[lchip]->buf_scan->port[lport].queue_en;
            wb_monitor_buf_scan->port_en_igs = p_usw_monitor_master[lchip]->buf_scan->port[lport].port_en_igs;
            wb_monitor_buf_scan->port_en_egs = p_usw_monitor_master[lchip]->buf_scan->port[lport].port_en_egs;
            wb_data.valid_cnt = 1;
            CTC_ERROR_GOTO(ctc_wb_add_entry(&wb_data), ret, done);
        }
        CTC_WB_SYNC_END_DATA(CTC_FEATURE_MONITOR, SYS_WB_APPID_MONITOR_SUBID_BUFF_SCAN_CTL);
    }

    user_data.data = &wb_data;
    user_data.value1 = lchip;
    if (p_usw_monitor_master[lchip]->p_monitor_hash)
    {
        /*syncup hash*/
        if (app_id == 0 || CTC_WB_SUBID(app_id) == SYS_WB_APPID_MONITOR_SUBID_PATH_LATENCY)
        {
            CTC_WB_INIT_DATA_T((&wb_data), sys_wb_monitor_path_latency_t, CTC_FEATURE_MONITOR, SYS_WB_APPID_MONITOR_SUBID_PATH_LATENCY);
            CTC_ERROR_GOTO(ctc_hash_traverse(p_usw_monitor_master[lchip]->p_monitor_hash,
                                                                    _sys_usw_monitor_path_wb_sync_func, &user_data), ret, done);
            if (wb_data.valid_cnt > 0)
            {
                CTC_ERROR_GOTO(ctc_wb_add_entry(&wb_data), ret, done);
                wb_data.valid_cnt = 0;
            }
            CTC_WB_SYNC_END_DATA(CTC_FEATURE_MONITOR, SYS_WB_APPID_MONITOR_SUBID_PATH_LATENCY);
        }
    }
done:
    MONITOR_UNLOCK;
    CTC_WB_FREE_BUFFER(wb_data.buffer);

    return ret;
}

int32
_sys_usw_monitor_wb_init(uint8 lchip)
{
   ctc_wb_appid_t  appid;
   sal_memset(&appid,0,sizeof(appid));

   appid.app_id = lchip << 16 | CTC_WB_APPID(CTC_FEATURE_MONITOR, SYS_WB_APPID_MONITOR_SUBID_MASTER) ;
   appid.entry_num = 1;
   appid.entry_size  = sizeof(sys_wb_monitor_master_t);
   ctc_wb_add_appid( lchip, &appid);

   appid.app_id = lchip << 16 | CTC_WB_APPID(CTC_FEATURE_MONITOR, SYS_WB_APPID_MONITOR_SUBID_PATH_LATENCY) ;
   appid.entry_num = SYS_MONITOR_MAX_VIEWID * SYS_MONITOR_MAX_VIEWID;
   appid.entry_size  = sizeof(sys_wb_monitor_path_latency_t);
   ctc_wb_add_appid( lchip, &appid);

   if (DRV_FROM_AT(lchip))
   {
        appid.app_id = lchip << 16 | CTC_WB_APPID(CTC_FEATURE_MONITOR, SYS_WB_APPID_MONITOR_SUBID_BUFF_SCAN_CTL) ;
        appid.entry_num = MAX_PORT_NUM_PER_CHIP;
        appid.entry_size  = sizeof(sys_wb_monitor_buf_scan_ctl_t);
        ctc_wb_add_appid( lchip, &appid);
   }

   return 0;
}


STATIC int32
_sys_usw_monitor_wb_restore(uint8 lchip)
{
    int32 ret = CTC_E_NONE;
    uint32 cmd = 0;
    uint32 entry_cnt = 0;
    uint16 index = 0;
    uint16 channel_id = 0;
    ds_t ds;
    uint8  step = 0;
    ctc_wb_query_t    wb_query;
    sys_wb_monitor_master_t wb_monitor_master;
    sys_wb_monitor_path_latency_t wb_path_lat;
    sys_wb_monitor_buf_scan_ctl_t wb_monitor_buf_scan;
    sys_monitor_path_config_t* p_path_cfg = NULL;
    ErmGlbMbCfg_m glb_mb_cfg;

    cmd = DRV_IOR(ErmGlbMbCfg_t, DRV_ENTRY_FLAG);
    CTC_ERROR_RETURN(DRV_IOCTL(lchip, 0, cmd, &glb_mb_cfg));
    step = ErmGlbMbCfg_sc_1_scMbMinThrd_f - ErmGlbMbCfg_sc_0_scMbMinThrd_f;
    for(index = 0; index < 4; index ++)
    {
        p_usw_monitor_master[lchip]->mb_thrd->sc_thrd[index][0] = GetErmGlbMbCfg(V, sc_0_scMbMinThrd_f + step * index, &glb_mb_cfg);
        p_usw_monitor_master[lchip]->mb_thrd->sc_thrd[index][1] = GetErmGlbMbCfg(V, sc_0_scMbMaxThrd_f + step * index, &glb_mb_cfg);
    }
    p_usw_monitor_master[lchip]->mb_thrd->total_thrd[0] = GetErmGlbMbCfg(V, totalMbMinThrd_f, &glb_mb_cfg);
    p_usw_monitor_master[lchip]->mb_thrd->total_thrd[1] = GetErmGlbMbCfg(V, totalMbMaxThrd_f, &glb_mb_cfg);
    p_usw_monitor_master[lchip]->mb_thrd->c2c_thrd[0] = GetErmGlbMbCfg(V, c2cMbMinThrd_f, &glb_mb_cfg);
    p_usw_monitor_master[lchip]->mb_thrd->c2c_thrd[1] = GetErmGlbMbCfg(V, c2cMbMaxThrd_f, &glb_mb_cfg);
    p_usw_monitor_master[lchip]->mb_thrd->critical_thrd[0] = GetErmGlbMbCfg(V, criticalMbMinThrd_f, &glb_mb_cfg);
    p_usw_monitor_master[lchip]->mb_thrd->critical_thrd[1] = GetErmGlbMbCfg(V, criticalMbMaxThrd_f, &glb_mb_cfg);

    /* restore CTC_MONITOR_BUFFER_PORT thrd */
    if (DRV_FROM_AT(lchip))
    {
        for(channel_id = 0; channel_id < MCHIP_CAP(SYS_CAP_MONITOR_MAX_CHANNEL); channel_id++)
        {
            uint16 sub_chan = 0;
            uint8 dp_id = 0;
            uint8 pp_id = 0;
            
            sys_usw_port_api_get_sub_chan_by_chan(lchip, 0, channel_id, &sub_chan, &pp_id, &dp_id);
            if (sub_chan >= MCHIP_CAP(SYS_CAP_PER_DP_PHY_CHANNEL_NUM))
            {
                continue;
            }
            cmd = DRV_IOR(DsErmPortMbCfg_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(SYS_PP_BASE(lchip) + pp_id, sub_chan, DRV_CMD_DP_EN(cmd, dp_id), &ds));
            p_usw_monitor_master[lchip]->mb_thrd->port_thrd[channel_id][0] = GetDsErmPortMbCfg(V, minThrd_f, &ds);
            p_usw_monitor_master[lchip]->mb_thrd->port_thrd[channel_id][1] = GetDsErmPortMbCfg(V, maxThrd_f, &ds);
        }
    }
    else
    {
        for(channel_id = 0; channel_id < MCHIP_CAP(SYS_CAP_MONITOR_MAX_CHANNEL); channel_id++)
        {
            cmd = DRV_IOR(DsErmPortMbCfg_t, DRV_ENTRY_FLAG);
            CTC_ERROR_RETURN(DRV_IOCTL(lchip, channel_id, cmd, &ds));
            p_usw_monitor_master[lchip]->mb_thrd->port_thrd[channel_id][0] = GetDsErmPortMbCfg(V, mbMinThrd_f, &ds);
            p_usw_monitor_master[lchip]->mb_thrd->port_thrd[channel_id][1] = GetDsErmPortMbCfg(V, mbMaxThrd_f, &ds);
        }
    }

    if(!DRV_FROM_TMM(lchip))
    {
        return CTC_E_NONE;
    }

    CTC_WB_ALLOC_BUFFER(&wb_query.buffer);

    /* restore master */
    CTC_WB_INIT_QUERY_T((&wb_query), sys_wb_monitor_master_t, CTC_FEATURE_MONITOR, SYS_WB_APPID_MONITOR_SUBID_MASTER);

    CTC_WB_QUERY_ENTRY_BEGIN((&wb_query));
        sal_memcpy(&wb_monitor_master, (uint8*)(wb_query.buffer) + entry_cnt * (wb_query.key_len + wb_query.data_len), wb_query.key_len + wb_query.data_len);
        entry_cnt++;
        if (CTC_WB_VERSION_CHECK(SYS_WB_VERSION_MONITOR, wb_monitor_master.version))
        {
            ret = CTC_E_VERSION_MISMATCH;
            goto done;
        }
        sal_memcpy(p_usw_monitor_master[lchip]->port_array[0], wb_monitor_master.port_array[0], sizeof(wb_monitor_master.port_array[0]));
        sal_memcpy(p_usw_monitor_master[lchip]->port_array[1], wb_monitor_master.port_array[1], sizeof(wb_monitor_master.port_array[1]));
        if (DRV_FROM_AT(lchip))
        {
            p_usw_monitor_master[lchip]->buf_scan->total_en_igs = wb_monitor_master.total_en_igs;
            p_usw_monitor_master[lchip]->buf_scan->total_en_egs = wb_monitor_master.total_en_egs;
            p_usw_monitor_master[lchip]->buf_scan->sc_en_igs = wb_monitor_master.sc_en_igs;
            p_usw_monitor_master[lchip]->buf_scan->sc_en_egs = wb_monitor_master.sc_en_egs;
            p_usw_monitor_master[lchip]->buf_scan->c2c_en_igs = wb_monitor_master.c2c_en_igs;
            p_usw_monitor_master[lchip]->buf_scan->c2c_en_egs = wb_monitor_master.c2c_en_egs;
            p_usw_monitor_master[lchip]->buf_scan->critical_en_igs = wb_monitor_master.critical_en_igs;
            p_usw_monitor_master[lchip]->buf_scan->critical_en_egs = wb_monitor_master.critical_en_egs;
            p_usw_monitor_master[lchip]->buf_scan->round_trip_en = wb_monitor_master.round_trip_en;
            p_usw_monitor_master[lchip]->buf_scan->span_en = wb_monitor_master.span_en;
        }
    CTC_WB_QUERY_ENTRY_END((&wb_query));

    if (DRV_FROM_AT(lchip))
    {
        /* restore buf_scan */
        entry_cnt = 0;
        CTC_WB_INIT_QUERY_T((&wb_query), sys_wb_monitor_buf_scan_ctl_t, CTC_FEATURE_MONITOR, SYS_WB_APPID_MONITOR_SUBID_BUFF_SCAN_CTL);

        CTC_WB_QUERY_ENTRY_BEGIN((&wb_query));
            sal_memcpy(&wb_monitor_buf_scan, (uint8*)(wb_query.buffer) + entry_cnt * (wb_query.key_len + wb_query.data_len), wb_query.key_len + wb_query.data_len);
            index = wb_monitor_buf_scan.lport;
            p_usw_monitor_master[lchip]->buf_scan->port[index].port_sc_en_igs = wb_monitor_buf_scan.port_sc_en_igs;
            p_usw_monitor_master[lchip]->buf_scan->port[index].port_sc_en_egs = wb_monitor_buf_scan.port_sc_en_egs;
            p_usw_monitor_master[lchip]->buf_scan->port[index].port_tc_en_igs = wb_monitor_buf_scan.port_tc_en_igs;
            p_usw_monitor_master[lchip]->buf_scan->port[index].port_tc_en_egs = wb_monitor_buf_scan.port_tc_en_egs;
            p_usw_monitor_master[lchip]->buf_scan->port[index].queue_en = wb_monitor_buf_scan.queue_en;
            p_usw_monitor_master[lchip]->buf_scan->port[index].port_en_igs = wb_monitor_buf_scan.port_en_igs;
            p_usw_monitor_master[lchip]->buf_scan->port[index].port_en_egs = wb_monitor_buf_scan.port_en_egs;
            entry_cnt++;
        CTC_WB_QUERY_ENTRY_END((&wb_query));
    }

    /* restore monitor hash */
    if (p_usw_monitor_master[lchip]->p_monitor_hash)
    {
        entry_cnt = 0;
        CTC_WB_INIT_QUERY_T((&wb_query), sys_wb_monitor_path_latency_t, CTC_FEATURE_MONITOR, SYS_WB_APPID_MONITOR_SUBID_PATH_LATENCY);
        CTC_WB_QUERY_ENTRY_BEGIN((&wb_query));
            sal_memcpy(&wb_path_lat, (uint8*)(wb_query.buffer) + entry_cnt * (wb_query.key_len + wb_query.data_len), wb_query.key_len + wb_query.data_len);
            entry_cnt++;
            p_path_cfg = mem_malloc(MEM_MONITOR_MODULE, sizeof(sys_monitor_path_config_t));
            if (NULL == p_path_cfg)
            {
                ctc_hash_free(p_usw_monitor_master[lchip]->p_monitor_hash);
                ret = CTC_E_NO_MEMORY;
                goto done;
            }
            p_path_cfg->src_lport = wb_path_lat.src_lport;
            p_path_cfg->dst_lport = wb_path_lat.dst_lport;
            ctc_hash_insert(p_usw_monitor_master[lchip]->p_monitor_hash, p_path_cfg);
        CTC_WB_QUERY_ENTRY_END((&wb_query));
    }
done:
   CTC_WB_FREE_BUFFER(wb_query.buffer);

    return ret;
}

int32
sys_usw_monitor_init(uint8 lchip, void * p_global_cfg)
{
    uint32 ii = 0;
    int32 ret = CTC_E_NONE;
    if (p_usw_monitor_master[lchip])
    {
        return CTC_E_NONE;
    }
    SYS_VCHIP_MASTER_INIT(lchip, p_usw_monitor_master, CTC_FEATURE_MONITOR);

    p_usw_monitor_master[lchip] =  (sys_monitor_master_t*)mem_malloc(MEM_MONITOR_MODULE, sizeof(sys_monitor_master_t));
    if (NULL == p_usw_monitor_master[lchip])
    {
        SYS_MONITOR_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " No memory \n");
        return CTC_E_NO_MEMORY;

    }

    sal_memset(p_usw_monitor_master[lchip], 0, sizeof(sys_monitor_master_t));

    if(DRV_FROM_TMM(lchip))
    {
        p_usw_monitor_master[lchip]->p_latency = mem_malloc(MEM_MONITOR_MODULE, sizeof(ctc_monitor_msg_t)*MCHIP_CAP(SYS_CAP_MONITOR_SYNC_CNT));
        if (NULL == p_usw_monitor_master[lchip]->p_latency)
        {
            SYS_MONITOR_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " No memory \n");
            ret = CTC_E_NO_MEMORY;
            goto error_return1;

        }

        /*one msg reserved for mburst_stats*/
        p_usw_monitor_master[lchip]->p_buffer = mem_malloc(MEM_MONITOR_MODULE, sizeof(ctc_monitor_msg_t)*(MCHIP_CAP(SYS_CAP_MONITOR_SYNC_CNT)+SYS_MONITOR_EXT_MSG_CNT_MAX));
        if (NULL == p_usw_monitor_master[lchip]->p_buffer)
        {
            SYS_MONITOR_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " No memory \n");
            ret = CTC_E_NO_MEMORY;
            goto error_return1_1;

        }

        if(DRV_FROM_AT(lchip))
        {
            /*one msg reserved for mburst_stats*/
            p_usw_monitor_master[lchip]->p_buffer_stats = mem_malloc(MEM_MONITOR_MODULE, sizeof(ctc_monitor_msg_t)*(MCHIP_CAP(SYS_CAP_MONITOR_SYNC_CNT)));
            if (NULL == p_usw_monitor_master[lchip]->p_buffer_stats)
            {
                SYS_MONITOR_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " No memory \n");
                ret = CTC_E_NO_MEMORY;
                goto error_return1_2;

            }
        }
    }
    else
    {
        /*one msg reserved for mburst_stats*/
        p_usw_monitor_master[lchip]->p_buffer = mem_malloc(MEM_MONITOR_MODULE, sizeof(ctc_monitor_msg_t)*(MCHIP_CAP(SYS_CAP_MONITOR_SYNC_CNT)*4+SYS_MONITOR_EXT_MSG_CNT_MAX));
        if (NULL == p_usw_monitor_master[lchip]->p_buffer)
        {
            SYS_MONITOR_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " No memory \n");
            ret = CTC_E_NO_MEMORY;
            goto error_return1;

        }
    }

    p_usw_monitor_master[lchip]->buffer_stats = mem_malloc(MEM_MONITOR_MODULE, MCHIP_CAP(SYS_CAP_PORT_NUM) * sizeof(uint32*));
    p_usw_monitor_master[lchip]->latency_stats = mem_malloc(MEM_MONITOR_MODULE, MCHIP_CAP(SYS_CAP_PORT_NUM) * sizeof(uint64*));
    p_usw_monitor_master[lchip]->mburst_stats = mem_malloc(MEM_MONITOR_MODULE, MCHIP_CAP(SYS_CAP_PORT_NUM) * sizeof(uint64*));
    p_usw_monitor_master[lchip]->mburst_timestamp = mem_malloc(MEM_MONITOR_MODULE, MCHIP_CAP(SYS_CAP_PORT_NUM) * sizeof(uint64));

    if (NULL == p_usw_monitor_master[lchip]->buffer_stats
        || NULL == p_usw_monitor_master[lchip]->latency_stats
        || NULL == p_usw_monitor_master[lchip]->mburst_stats
        || NULL == p_usw_monitor_master[lchip]->mburst_timestamp)
    {
        SYS_MONITOR_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " No Memory\n");
        ret = CTC_E_NO_MEMORY;
        goto error_return2;
    }
    sal_memset(p_usw_monitor_master[lchip]->buffer_stats, 0, MCHIP_CAP(SYS_CAP_PORT_NUM) * sizeof(uint32*));
    sal_memset(p_usw_monitor_master[lchip]->latency_stats, 0, MCHIP_CAP(SYS_CAP_PORT_NUM) * sizeof(uint64*));
    sal_memset(p_usw_monitor_master[lchip]->mburst_stats, 0, MCHIP_CAP(SYS_CAP_PORT_NUM) * sizeof(uint64*));
    sal_memset(p_usw_monitor_master[lchip]->mburst_timestamp, 0, MCHIP_CAP(SYS_CAP_PORT_NUM) * sizeof(uint64));

    for (ii = 0; ii < MCHIP_CAP(SYS_CAP_CHANNEL_NUM); ii++)
    {
        p_usw_monitor_master[lchip]->buffer_stats[ii] = mem_malloc(MEM_MONITOR_MODULE, CTC_BOTH_DIRECTION * sizeof(uint32));
        p_usw_monitor_master[lchip]->latency_stats[ii] = mem_malloc(MEM_MONITOR_MODULE, CTC_MONITOR_LATENCY_THRD_LEVEL * sizeof(uint64));
        p_usw_monitor_master[lchip]->mburst_stats[ii] = mem_malloc(MEM_MONITOR_MODULE, CTC_MONITOR_LATENCY_THRD_LEVEL * sizeof(uint64));
        if (NULL == p_usw_monitor_master[lchip]->latency_stats[ii]
            || NULL == p_usw_monitor_master[lchip]->buffer_stats[ii]
            || NULL == p_usw_monitor_master[lchip]->mburst_stats[ii])
        {
            SYS_MONITOR_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " No Memory\n");
            ret = CTC_E_NO_MEMORY;
            goto error_return3;
        }
        sal_memset(p_usw_monitor_master[lchip]->buffer_stats[ii], 0, CTC_BOTH_DIRECTION * sizeof(uint32));
        sal_memset(p_usw_monitor_master[lchip]->latency_stats[ii], 0, CTC_MONITOR_LATENCY_THRD_LEVEL * sizeof(uint64));
        sal_memset(p_usw_monitor_master[lchip]->mburst_stats[ii], 0, CTC_MONITOR_LATENCY_THRD_LEVEL * sizeof(uint64));
    }
    if (DRV_FROM_AT(lchip))
    {
        p_usw_monitor_master[lchip]->buf_scan = mem_malloc(MEM_MONITOR_MODULE, sizeof(sys_monitor_buf_scan_ctl_t));
        if (NULL == p_usw_monitor_master[lchip]->buf_scan)
        {
            SYS_MONITOR_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " No Memory\n");
            ret = CTC_E_NO_MEMORY;
            goto error_return4;
        }
        sal_memset(p_usw_monitor_master[lchip]->buf_scan, 0, sizeof(sys_monitor_buf_scan_ctl_t));
    }
    p_usw_monitor_master[lchip]->mb_thrd = mem_malloc(MEM_MONITOR_MODULE, sizeof(sys_monitor_mb_thrd_t));
    if (NULL == p_usw_monitor_master[lchip]->mb_thrd)
    {
        SYS_MONITOR_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " No Memory\n");
        ret = CTC_E_NO_MEMORY;
        goto error_return5;
    }
    sal_memset(p_usw_monitor_master[lchip]->mb_thrd, 0, sizeof(sys_monitor_mb_thrd_t));

    ret = sal_mutex_create(&(p_usw_monitor_master[lchip]->p_mutex));
    if (ret || !(p_usw_monitor_master[lchip]->p_mutex))
    {
        SYS_MONITOR_DBG_OUT(CTC_DEBUG_LEVEL_ERROR, " Create mutex fail\n");
        ret = CTC_E_NO_MEMORY;
        goto error_return5_1;
    }

    CTC_ERROR_GOTO( sys_usw_monitor_set_timer(lchip, CTC_MONITOR_BUFFER, 1000), ret, error_return6);
    CTC_ERROR_GOTO( sys_usw_monitor_set_timer(lchip, CTC_MONITOR_LATENCY, 1), ret, error_return6);

    CTC_ERROR_GOTO(sys_usw_monitor_init_global(lchip, p_global_cfg), ret, error_return6);

    CTC_ERROR_GOTO(sys_usw_dma_register_cb(lchip, SYS_DMA_CB_TYPE_MONITOR, MCHIP_MON(lchip)->sync_data), ret, error_return6);

    if (!p_usw_monitor_master[lchip]->func)
    {
        sys_usw_monitor_register_cb(lchip, sys_usw_monitor_process_isr, NULL);
    }


    if (MCHIP_MON(lchip)->init)
    {
        MCHIP_MON(lchip)->init(lchip);
    }

    /* warmboot register */
    CTC_ERROR_GOTO(sys_usw_wb_sync_register_cb(lchip, CTC_FEATURE_MONITOR,SYS_WB_APPID_MONITOR_SUBID_MAX, _sys_usw_monitor_wb_sync), ret, error_return6);

    /* warmboot data restore */
    if (CTC_WB_ENABLE(lchip) && (CTC_WB_STATUS(lchip) == CTC_WB_STATUS_RELOADING))
    {
        CTC_ERROR_GOTO(_sys_usw_monitor_wb_restore(lchip), ret, error_return6);
    }

    if (CTC_WB_ENABLE(lchip))
    {
        _sys_usw_monitor_wb_init(lchip);
    }
    sys_usw_mchip_set_feature_en(lchip,CTC_FEATURE_MONITOR);
    return CTC_E_NONE;

error_return6:
    sal_mutex_destroy(p_usw_monitor_master[lchip]->p_mutex);
error_return5_1:
    mem_free(p_usw_monitor_master[lchip]->mb_thrd);
error_return5:
    mem_free(p_usw_monitor_master[lchip]->buf_scan);
error_return4:
    ii = MCHIP_CAP(SYS_CAP_CHANNEL_NUM) - 1;
error_return3:
    do{
        mem_free(p_usw_monitor_master[lchip]->buffer_stats[ii]);
        mem_free(p_usw_monitor_master[lchip]->latency_stats[ii]);
        mem_free(p_usw_monitor_master[lchip]->mburst_stats[ii]);
        if (0 == ii)
        {
            break;
        }
        ii--;
    }while(1);
error_return2:
    mem_free(p_usw_monitor_master[lchip]->buffer_stats);
    mem_free(p_usw_monitor_master[lchip]->latency_stats);
    mem_free(p_usw_monitor_master[lchip]->mburst_stats);
    mem_free(p_usw_monitor_master[lchip]->mburst_timestamp);
    mem_free(p_usw_monitor_master[lchip]->p_buffer);
error_return1_2:
    if(DRV_FROM_AT(lchip))
    {
        mem_free(p_usw_monitor_master[lchip]->p_buffer);
    }
error_return1_1:
    if(DRV_FROM_TMM(lchip))
    {
        mem_free(p_usw_monitor_master[lchip]->p_latency);
    }
error_return1:
    mem_free(p_usw_monitor_master[lchip]);

    return ret;

}



int32
sys_usw_monitor_deinit(uint8 lchip)
{
    uint32 ii = MCHIP_CAP(SYS_CAP_CHANNEL_NUM) - 1;
    LCHIP_CHECK(lchip);
    if (NULL == p_usw_monitor_master[lchip])
    {
        return CTC_E_NONE;
    }
    SYS_VCHIP_MASTER_DEINIT(lchip, p_usw_monitor_master, CTC_FEATURE_MONITOR);

    sys_usw_dma_register_cb(lchip, SYS_DMA_CB_TYPE_MONITOR, NULL);
    sys_usw_wb_sync_register_cb(lchip, CTC_FEATURE_MONITOR, 0,NULL);

    if (MCHIP_MON(lchip)->deinit)
    {
        MCHIP_MON(lchip)->deinit(lchip);
    }
    sal_mutex_destroy(p_usw_monitor_master[lchip]->p_mutex);
    do{
        mem_free(p_usw_monitor_master[lchip]->buffer_stats[ii]);
        mem_free(p_usw_monitor_master[lchip]->latency_stats[ii]);
        mem_free(p_usw_monitor_master[lchip]->mburst_stats[ii]);
        if (0 == ii)
        {
            break;
        }
        ii--;
    }while(1);
    mem_free(p_usw_monitor_master[lchip]->buffer_stats);
    mem_free(p_usw_monitor_master[lchip]->latency_stats);
    mem_free(p_usw_monitor_master[lchip]->mburst_stats);
    mem_free(p_usw_monitor_master[lchip]->mburst_timestamp);

    if(DRV_FROM_TMM(lchip))
    {
        mem_free(p_usw_monitor_master[lchip]->p_latency);
    }
    if(DRV_FROM_AT(lchip))
    {
        mem_free(p_usw_monitor_master[lchip]->p_buffer_stats);
    }
    mem_free(p_usw_monitor_master[lchip]->p_buffer);
    mem_free(p_usw_monitor_master[lchip]->buf_scan);
    mem_free(p_usw_monitor_master[lchip]->mb_thrd);
    mem_free(p_usw_monitor_master[lchip]);

    return CTC_E_NONE;
}

#endif

